A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier

Abstract

The design of a 2.4-GHz fully integrated 61 fractional-frequency synthesizer in 0.35-m CMOS process is presented. The design focuses on the prescaler and the loop filter, which are often the speed and the integration bottlenecks of the phase-locked loop (PLL), respectively. A 1.5-V 3-mW inherently glitch-free phase-switching prescaler is proposed. It is based on eight lower frequency 45 -spaced phases and a reversed phase-switching sequence. The large integrating capacitor in the loop filter was integrated on chip via a simple capacitance multiplier that saves silicon area, consumes only 0.2 mW, and introduces negligible noise. The synthesizer has a 9.4% frequency tuning range from 2.23 to 2.45 GHz. It dissipates 16 mW and takes an active area of 0.35 mm 2 excluding the 0.5-mm 2 digital 61 modulator. Index Terms-Capacitance multiplier, CMOS, fractional-, frequency synthesizer, loop filter, phase-switching prescaler, phase-locked loop (PLL), sigma-delta (61). worked on IC design in Zhuhai, China. In the summer and fall of 2000, he worked on PLL design as a Co-op Student at Texas Instruments Incorporated, Dallas, TX. His research interests include analog/RF and mixed-signal circuits design.

Performance Estimation of SVL technique based ½ frequency divider in 45nm CMOS technology

“…Injection locked frequency dividers utilize an oscillator whose center frequency is locked to harmonic incoming signal frequency [4]. The ½ frequency divider employs two D latches in a master slave configuration with negative feedback [2]. While dynamic and injection-locked dividers can attain high frequencies at low power consumption.…”

Design and Performance Estimation of low Power Frequency Divider in 45nm CMOS Technology

“…Totrim down battery size, the power consumption of PLL, consumes the largest amount of power in wireless front end, needs to reduce. Injection-locked divider (ILD) uses output frequency of oscillator and modulated with a frequency mixer this realizes high operations of frequency along with low power consumption [2][3]. On other hand HILDs using a ring oscillator instead of an LC resonator [4,5] consume relatively large amount of power but exhibit narrow locking range.…”

A low power CMOS phase-switching prescaler for 1.8–2.4 GHz wireless communications

“…For the frequency divider, it must be programmable for channelselection in multi-channel communication systems. Therefore, a dual-modulus prescaler is needed to provide variable division ratios [1][2][3]. Phase switching technique, as shown in Fig.…”

“…Phase switching technique, as shown in Fig. 1, has been proposed to obtain a lower power consumption for its simplified topology at high frequency [2][3]. Since the change of modulus is obtained by switching among different phase signals, the prescaler requires a high-speed multi-phase clock generator at the highest speed.…”

“…Since the change of modulus is obtained by switching among different phase signals, the prescaler requires a high-speed multi-phase clock generator at the highest speed. This generator is usually implemented with the MOS Current Mode Logic (MCML), which takes the most important portion of total power consumption [3]. The MCML circuit is able to operate at a very high frequency but has a large static power consumption at GHz ranges.…”