A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment

Lee, Tzung-Je; Su, Wen-Jian; Tolentino, Lean Karlo S.; Wang, Chua-Chin

doi:10.1109/apccas51387.2021.9687736

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A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment

Cited by 5 publications

References 7 publications

GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process

GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process

A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process

Using Machine Learning Techniques to Determine DDR5 SDRAM I/O Buffer’s Slew Rate at Different PVT Variations

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