A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background Offset and Timing-Skew Calibration

Seong, Kiho; Han, Jae-Soub; Shim, Yong; Baek, Kwang‐Hyun

doi:10.1109/tcsii.2022.3188290

Cited by 5 publications

(4 citation statements)

References 14 publications

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“…Based on the outcomes and mathematical expressions presented in equations (9) through (24), it is possible to derive the following deductions: Enhancing the sizes can effectively decrease the comparator's static offset resulting from M9 and M10, as the variance of s ∆V (SFDR) are 59.16 dB as well as 64.02 dB, correspondingly. The resultant value for the effective number of bits (ENOB) is 9.53 bits.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…The ADC obtains a SNDR of 58.1 dB and a SFDR of 72.1 dB using an 80-MHz input. Seong et al [24] introduced the on-chip background offset. A comparator offset is used to compensate clocked edge mismatch for sub-ADC sampling harmonic distortion and the circuit achieved SNDR of 40 dB in Nyquist input while consuming 7.57 mW, resulting in a FoM of 37.2 fJ/conversion-step.…”

Section: Introductionmentioning

confidence: 99%

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Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

Tyagi,

Mittal,

Kumar

2023

Phys. Scr.

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The utilisation of low power SAR (Successive Approximation Register) Analog-to-Digital Converters holds significant importance in the domain of bio-medical signal acquisition. The present study showcases the utilisation of an 8-bit CMOS SAR-ADC for integration into the analog front end of bio-signal acquisition. The focus of this technology pertains to the monitoring of implanted bio-signal devices, with a specific emphasis on ECG/EEG signals. A capacitive digital-to-analog converter (DAC) is suggested as a means to attain power consumption in the microwatt range. This approach enables comparisons to be made without any energy consumption, leading to a substantial enhancement in energy efficiency. Furthermore, a comprehensive theoretical examination of comparator offset voltages has been conducted to enhance the offset performance of the comparator operating at low supply voltage. The analysis indicates that optimization of the comparator is achieved solely through the adjustment of transistor sizes, without the implementation of any specific offset cancellation techniques. Simulations indicate that the optimization of the offset voltage to approximately 5 mV occurs when there is variation in the common-mode input voltage at a 1 V supply. The proposed Analog-to-Digital Converter (ADC) layout has been successfully executed utilizing the 45 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The Analog-to-Digital Converter (ADC) attains a Spurious-Free Dynamic Range (SFDR) of 64.02 dB and consumes 1.9 μW of power at a sampling rate of 1.1 MHz and a supply voltage of 1 V.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

Tyagi,

Mittal,

Kumar

2023

Phys. Scr.

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“…Seong and colleagues (17) introduced a method to address mismatches in sub-ADC sampling distortion due to harmonics. They also proposed two modes for calibrating the comparator offset: global offset and local offset.…”

Section: Literature Reviewmentioning

confidence: 99%

Design of CMOS 45nm SAR ADC for ECG Signal Applications

Pradeep,

Ramashri

2024

Preprint

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Efficient SAR ADCs are necessary for acquiring biomedical signals. The research highlights the use of an 8-bit CMOS 45nm SAR-ADC to capture bio-signals. A suggestion is put forward in the study to incorporate a DAC to improve energy efficiency at the nanowatt level. This approach allows for comparisons to be made with zero energy consumption, resulting in a significant improvement in energy utilization. Research indicates that optimizing the comparator can be achieved by adjusting transistor sizes, eliminating the need for specific offset cancelling methods. The 45nm CMOS technological node is effectively utilized in implementing the SAR-ADC architecture. The ADC achieves an SFDR of 64.12 dB with a power consumption of 1.89uW, operating at a sampling frequency of 1.1MHz and a voltage supply of 1V.

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“…In Hamidreza et al, 16 Meng et al 17 and Mingqiang et al, 12 the least mean square (LMS) method is used to accomplish the timing skew detection, but this method has a long estimation time for timing skews. In Kiho et al, 18 Jeonggoo et al, 19 Jianwei et al, 20 and Kiho et al, 21 the window detector (WD) is used to complete timing skew calibrations. An extra clock signal with the same frequency as the sampling frequency of the entire TIADC system is needed to drive this WD, such a high frequency clock signal is difficult to achieve in practice, and this contradicts the original intention of using the time interleaved sampling technique to enhance the sampling frequency of ADCs.…”

Section: Introductionmentioning

confidence: 99%

An 18‐bit 1‐GS/s time interleaved analog‐to‐digital converter with timing skew calibration based on an adaptive genetic algorithm

Zhao

Zhang

et al. 2023

Circuit Theory & Apps

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SummaryA foreground calibration method for timing skews of the time interleaved analog‐to‐digital converter (TIADC) system is proposed in this paper. In this method, the adaptive genetic algorithm (AGA) is used to replace the traditional least mean square (LMS) method to detect the timing skews, and the variable delay lines are used to calibrate the timing skews. This method can accomplish the detection and calibration of positive and negative timing skews, and the reference channels are not required. In addition, compared with other methods, this method has higher detection speed and detection accuracy. In this paper, a four‐channel 18‐bit 1‐GS/s TIADC system is modeled, and the performance of the proposed method is further verified. The results show that the convergence speed and the calibration accuracy of this method are higher, the signal‐to‐noise ratio (SNR) of the TIADC system is improved by 65.9 dB after calibration, and this method is also effective when the frequency of the input signal is close to the Nyquist frequency.

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A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background Offset and Timing-Skew Calibration

Cited by 5 publications

References 14 publications

Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

Design of CMOS 45nm SAR ADC for ECG Signal Applications

An 18‐bit 1‐GS/s time interleaved analog‐to‐digital converter with timing skew calibration based on an adaptive genetic algorithm

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