Ultra-wideband (UWB) wireless communication is prospering as a powerful partner of the Internet-of-things (IoT). Due to the ongoing development of UWB wireless communications, the demand for high-speed and medium resolution analog-to-digital converters (ADCs) continues to grow. The successive approximation register (SAR) ADCs are the most powerful candidate to meet these demands, attracting both industries and academia. In particular, recent time-interleaved SAR ADCs show that multi-giga sample per second (GS/s) can be achieved by overcoming the challenges of high-speed implementation of existing SAR ADCs. However, there are still critical issues that need to be addressed before the time-interleaved SAR ADCs can be applied in real commercial applications. The most well-known problem is that the time-interleaved SAR ADC architecture requires multiple sub-ADCs, and the mismatches between these sub-ADCs can significantly degrade overall ADC performance. And one of the most difficult mismatches to solve is the sampling timing skew. Recently, research to solve this timing-skew problem has been intensively studied. In this paper, we focus on the cutting-edge timing-skew calibration technique using a window detector. Based on the pros and cons analysis of the existing techniques, we come up with an idea that increases the benefits of the window detector-based timing-skew calibration techniques and minimizes the power and area overheads. Finally, through the continuous development of this idea, we propose a timing-skew calibration technique using a comparator offset-based window detector. To demonstrate the effectiveness of the proposed technique, intensive works were performed, including the design of a 7-bit, 2.5 GS/s 5-channel time-interleaved SAR ADC and various simulations, and the results prove excellent efficacy of signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 40.79 dB and 48.97 dB at Nyquist frequency, respectively, while the proposed window detector occupies only 6.5% of the total active area, and consumes 11% of the total power.

In this paper, a low power asynchronous successive approximation register (SAR) analog-todigital converter (ADC) involving the process, voltage, and temperature (PVT) compensation is presented. A proposed adaptive conversion time detection-and-control technique enhances the power efficiency, covering wide PVT variations. The proposed detection-and-control technique senses PVT variation in an aspect of conversion time, and adaptively controls the operation speed and power consumption. For PVT compensation, the proposed architecture includes the local supply/ground voltage. The local supply/ground voltage makes high |VGS| for transistors in the comparator and capacitive digital-to-analog converter switches, resulting in enhanced operation speed. However, when PVT condition changes to be favorable for the conversion speed, the |VGS| decreases for low power consumption. 30 chips were measured to verify the proposed ADC. Having the proposed architecture tested with 10 kHz input frequency, SNDR remained higher than 60 dB at unfavorable conditions such as-9 % supply voltage variation, or-20 ⁰C temperature variation. On the other hand, at favorable conditions such as +9 % supply voltage variation, or 80 ⁰C temperature variation, the power consumption of SAR ADC decreased without performance degradation. INDEX TERMS Asynchronous, compensation, low power, process voltage temperature (PVT), successive approximation register (SAR) analog-to-digital converter (ADC)

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Due to the advantages of fast frequency shifting, continuous phase shifting, fine frequency resolution, large bandwidth, and excellent spectral purity, the direct digital frequency synthesis (DDFS) technique is attracting more attention than ever before. Although the DDFS suffer from high power consumption, recent researches on the development of the low power DDFS (LP-DDFS) increases the feasibility of applying the DDFS to portable devices. To further accelerate the use of LP-DDFS, a new LP-DDFS design to significantly improve power efficiency is proposed and analyzed in this paper. In the new design, the dominant spur by truncation errors causing performance degradation has been also thoroughly considered. Since the existing dithering techniques for the truncation error problems can cause the additional performance degradation due to the side effects such as frequency offset and SNDR deterioration, an enhanced dithering technique is also proposed in this paper. The proposed technique includes a frequency compensation circuit and thus minimizes the truncation errors in the LP-DDFS with the minimal additional power consumption and SNDR degradation. Both theoretical and experimental analysis are conducted to verify the proposed design, where a prototype chip is fabricated and measured. INDEX TERMS Direct digital frequency synthesizer (DDFS/DDS), dithering scheme, high spuriousfree dynamic range (SFDR), low power design, Phase accumulator (PACC), pseudo-random binary sequence (PRBS).

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