Proceedings of CICC 97 - Custom Integrated Circuits Conference
DOI: 10.1109/cicc.1997.606611
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A 2.5-V, 1-W monolithic CMOS RF power amplifier

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Cited by 66 publications
(18 citation statements)
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“…As a consequence, the output power given by (18) will not be maximized. This means that this design differs from earlier CMOS power amplifiers [6], [10], whose primary goal was to achieve a high output power. The following values were used to calculate the output power and the efficiency: V; ; ; nH; ; nH ; ; ;…”
Section: Combining the Efficienciesmentioning
confidence: 99%
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“…As a consequence, the output power given by (18) will not be maximized. This means that this design differs from earlier CMOS power amplifiers [6], [10], whose primary goal was to achieve a high output power. The following values were used to calculate the output power and the efficiency: V; ; ; nH; ; nH ; ; ;…”
Section: Combining the Efficienciesmentioning
confidence: 99%
“…After rearranging the terms in the above equation, we come to (9) and the actual load resistance can therefore be written as (10) Substituting in (7) by the actual load resistance gives…”
Section: A Inductor Lossesmentioning
confidence: 99%
“…For RF power amplifiers, only a few CMOS circuits have been implemented. In [4] a switchtype 1-W CMOS power amplifier having a power added efficiency of 42% at 2.5 V supply voltage was reported. The low breakdown voltage and the strongly nonlinear parasitic drain-to-bulk output capacitance have made it difficult to implement conventional high efficiency power amplifiers with standard CMOS technology.…”
Section: Introductionmentioning
confidence: 98%
“…These works initially focused on more or less linear amplifier structures such as class A, AB, B or C, but research has since then focused more on the switched-mode class-D, E and F, as higher clocking or switching speeds became available with improvements in CMOS technology. Su and McFarland (1997) presented a 0.8µm CMOS SM amplifier consisting of four stages with the final stage in switched-mode. A Power-Added Efficiency (PAE) of 42% was achieved at 850MHz with a 2.5V supply, and largely off-chip input and output matching networks were used.…”
Section: Cmos Pa Implementationsmentioning
confidence: 99%