Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94
DOI: 10.1109/isscc.1994.344632
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A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM

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Cited by 7 publications
(7 citation statements)
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“…The octaphase clocks from the PLL are applied to the voltage-controlled delay line (VCDL) whose delay is controlled by the CDR loop to locate the edges of the octaphase clocks at the center of the received-data window. For correct operation of the 1/8-rate linear PD, the duty cycles of the VCDL outputs are adjusted to be 50% by the analog duty-cycle corrector [8].…”
Section: Architecture Of Cdrmentioning
confidence: 99%
“…The octaphase clocks from the PLL are applied to the voltage-controlled delay line (VCDL) whose delay is controlled by the CDR loop to locate the edges of the octaphase clocks at the center of the received-data window. For correct operation of the 1/8-rate linear PD, the duty cycles of the VCDL outputs are adjusted to be 50% by the analog duty-cycle corrector [8].…”
Section: Architecture Of Cdrmentioning
confidence: 99%
“…A DLL relying on quadrature phase mixing [3] has been proposed to overcome the limited range problem of the conventional DLL. The phase mixing technique using quadrature clocks provides unlimited phase shift capability.…”
Section: (B)mentioning
confidence: 99%
“…(2) The sensitivity of over to process variations should be analyzed to guarantee a reliable operation. For example, the sensitivity to the threshold voltage variation of the transistor can be obtained by (3), shown at the bottom of the page. In (3), means of transistor .…”
Section: A Low-jitter Schemementioning
confidence: 99%
“…Practically this is challenging, as the current produced by a current source as shown in Another way to realize variable delay is by phase interpolation, which can be implemented using current sources [18][19], resistors [20][21] or delay lines [22]. The basic concept of interpolation and example waveforms are shown in Fig.…”
Section: Introductionmentioning
confidence: 99%