A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

Ru, Jiayoon; Palattella, Claudia; Geraedts, P.F.J.; Klumperink, Eric A.M.; Nauta, Bram

doi:10.1109/jssc.2015.2414421

Cited by 89 publications

(51 citation statements)

References 27 publications

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“…Measured standard deviation in the delay line was σ D = 0.22LSB; this value is used in the next section to model the impact of delay‐line mismatch in the modulation algorithms. Although the target of referred work was to achieve high time resolution with operating frequencies in the range of some MHz, resolutions in the order of sub‐picoseconds have been reported using standards CMOS technologies …”

Section: Circuit Level Considerationsmentioning

confidence: 99%

Table‐based PWM for all‐digital RF transmitters

Morales

Chierchie

Mandolesi

et al. 2018

Circuit Theory & Apps

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Summary In this paper, a novel pulse‐width modulator (PWM) for an all‐digital PWM transmitter based on switching amplification is presented. In this approach, each symbol is represented by a sequence of pre‐computed PWM pulse widths stored in a table that results in reduced error vector magnitude (EVM). A high‐resolution pulse former is then used to build the bipolar radio frequency (RF) signal. Simulations and comparisons to other approaches reported in the literature under different oversampling ratios and finite time resolutions are presented. The impact of nonlinearities in the variable duty‐cycle generator is also analyzed to demonstrate the robustness of the proposed technique.

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Section: Circuit Level Considerationsmentioning

confidence: 99%

Table‐based PWM for all‐digital RF transmitters

Morales

Chierchie

Mandolesi

et al. 2018

Circuit Theory & Apps

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“…We actually developed this INL measurement method to allow for measuring the INL of a record high-resolution DTC that exploits the constant slope principle [15], and implemented in the 65-nm CMOS technology. Measuring the DTC with an on-chip digital-to-analog converter (DAC) using the direct method failed because of the DTC resolution on the order of tens of femtoseconds.…”

Section: Measurementsmentioning

confidence: 99%

“…Measured delay step produced by the DTC[15] as a function of the upper voltage of the modulating square waves, with 50 repetitions for each delay.…”

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confidence: 99%

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A Sensitive Method to Measure the Integral Nonlinearity of a Digital-to-Time Converter Based on Phase Modulation

Palattella

Klumperink

et al. 2015

IEEE Trans. Circuits Syst. II

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A digital-to-time converter (DTC) produces a time delay based on a digital code. Similar to data converters, linearity is a key metric for a DTC and it can be characterized by its integral nonlinearity (INL). However, measuring the INL of a subpicosecond-resolution DTC is problematic, even when using the best available high-speed oscilloscopes. In this brief we propose a new method to measure the INL of a DTC by applying digital phase modulation and measuring the output spectrum with a spectrum analyzer. The frequency selectivity of this method allows for an improved measurement resolution down to a few femtoseconds and allows measuring an INL below 100 fs. The proposed method is verified by behavioral simulations and is employed to measure the INL of a high-resolution DTC realized in the 65-nm CMOS, with a time resolution of 25 fs and a standard deviation of 27 fs.

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“…They can be used in clock-and-data-recovery (CDR) circuits [1,2], in the feedback or reference path of a phase-locked loop (PLL) [3,4] or as direct phase modulators in outphasing transmitters (OT) [5]. While DTCs in PLLs often operate close to the reference oscillator frequency, CDR and OT DTCs are required to operate at frequencies in the GHz range.…”

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confidence: 99%

2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS

Sievert

Degani

Ben-Bassat

et al. 2016

2016 IEEE International Solid-State Circuits Conference (ISSCC)

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Digital-to-time converters (DTC) generate a clock with a time delay (or phase shift) based on a digital input code. They can be used in clock-and-data-recovery (CDR) circuits [1,2], in the feedback or reference path of a phase-locked loop (PLL) [3,4] or as direct phase modulators in outphasing transmitters (OT) [5]. While DTCs in PLLs often operate close to the reference oscillator frequency, CDR and OT DTCs are required to operate at frequencies in the GHz range. DTCs are often built using a multistage segmented architecture, employing separate coarse and fine delay tuning.Coarse tuning is usually implemented using multiphase generators based on delay-locked loops (DLLs) [5] or dividers [1], followed by a multiplexer (MUX). Compared to DLLs, dividers do not require a control loop and can achieve lower jitter, but their input clock frequency has to be a multiple of the output frequency. The fine tuning is commonly implemented either with delay cells [4,5], which tune the RC constant of a node to modify the signal zero crossing time, or with phase interpolators (PI) [1]. While delay cells offer high linearity, they cause unwanted supply modulation through a code-dependent current consumption, high jitter through the degradation of the (dis)charge slopes, and do not provide a well-defined delay range. Replica paths with inverted codes are necessary to equalize the current consumption over code [4] and calibration engines are used to cope with the undefined range [5]. PIs on the other hand can provide a full and exact 2π coverage, but have intrinsically high nonlinearity [1,2,6], caused mainly by (a) the ratio Δt/τ int of temporal spacing of the two input signals Δt and the time constant at the interpolation node τ int [2,6] and (b) contention between different interpolation cells (INTC), which leads to short-circuit (cross) currents between V DD and V SS during the interpolation [6]. Harmonic rejection filtering has been introduced to improve the PI linearity [1], but at expense of a lower slew rate of the internal signals and hence jitter.To achieve a wide range (500ps) with fine resolution (244fs), a full and exact 2π coverage, low jitter and high linearity, this paper presents a DTC incorporating: (a) a multi-modulus-divider (MMD) coarse-tuning stage for 2π coverage, (b) re-sampling of the coarse stage by rising and falling edges of the input clock for low-jitter, (c) a PI-based fine-tuning stage for correct-by-construction coverage, (d) embedding additional logic inside the INTCs to break the contention cross-currents for high linearity. The current consumption of the DTC is equal over all codes, resulting in lower sensitivity to the power supply impedance and avoiding replica paths. Figure 2.9.1 shows the DTC architecture. It is segmented into 3 stages, that produce successively finer time resolution: in an ultra-coarse tuning stage, an MMD with a 3b resolution produces 2 output signals at 2GHz spaced by Δt uc = T out /8 = 62.5ps, a coarse-tuning stage reduces this spacing with a 1b resolution to Δt c = 31.25p...

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A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

Cited by 89 publications

References 27 publications

Table‐based PWM for all‐digital RF transmitters

Table‐based PWM for all‐digital RF transmitters

A Sensitive Method to Measure the Integral Nonlinearity of a Digital-to-Time Converter Based on Phase Modulation

2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS

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