A 2.7 ns 0.25 μm CMOS 54×54 b multiplier

Hagihara, Yoshihiro; Inui, S.; Yoshikawa, Atsushi; Nakazato, S.; Iriki, S.; Ikeda, R.; Shibue, Y.; Inaba, Tsuginori; Kagamihara, M.; Yamashina, M.

doi:10.1109/isscc.1998.672473

Cited by 5 publications

(8 citation statements)

References 5 publications

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“…The latency of the proposed multiplier is 1.88ns with a 1.8V supply. The multiplication time of the proposed multiplier is reduced to 84% in comparison with that of the fastest-available conventional multiplier [4], even when the process technologies for both multipliers are normalized to 0.25µm CMOS. Figure 11 shows the chip layout of the proposed multiplier.…”

Section: Design Of a Crosstalk-noise-free Sd Full Addermentioning

confidence: 99%

“…Since the performance of the floatingpoint multiplier depends primarily on that of the mantissa part, the development of a high-performance 54x54-bit multiplier macro for mantissa multiplication is a critical issue in the recent deep-submicron VLSI era [1]- [4]. On the other hand, as technology scales into the nanometer regime, the immunity of interconnect crosstalk noise is becoming a metric of comparable importance to area, speed, and power in VLSI systems [5].…”

Section: Introductionmentioning

confidence: 99%

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A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry

Mochizuki

Hanyu

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

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This paper presents a new 54×54-bit multiplier using fully differential-pair circuits (DPCs). The DPC is a key component in maintaining an input signal-voltage swing of 0.2V while providing a large current-driving capability. The combination of the DPC and the multi-level current-mode linear summation makes critical-path delay and transistor counts reduced, which achieves 1.88ns latency with 74.2mW from a 1.8V supply on a 0.85mm 2 die. It is also discussed about the efficiency of the DPCs for crosstalk noise reduction.

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Section: Design Of a Crosstalk-noise-free Sd Full Addermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry

Mochizuki

Hanyu

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

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“…So far, CMOS circuits with dynamic operation, such as the domino circuit, have been widely used as arithmetic circuits for high-speed processors [5], [6]. In the proposed circuit, a pre-charge control signal, CK, and its inverse signal, CKB, control the gates of two pre-charged transistors, MPSW1 and MNSW1, and the output terminal, OUT, is pre-charged to signal level 0 (VDD1).…”

Section: Sd-cmos Logic Circuitmentioning

confidence: 99%

“…Though we previously proposed a signed-digit CMOS (SD-CMOS) logic circuit with static operation and a multi-voltage power supply [3], the proposed circuit did not have sufficient advantages, in terms of either operation speed or element number, over redundant binary digital circuits using normal binary (NB) CMOS gates [4]. In this paper, we propose a dynamic CMOS circuit design methodology, which we have adopted in various arithmetic circuits used with general processors [5], [6]. As examples indicating improved operation with the new design, we demonstrate a driver circuit, an inverter circuit, a full-adder circuit, and a parallel multiplier circuit.…”

Section: Introductionmentioning

confidence: 99%

Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation

Fukuda

35th International Symposium on Multiple-Valued Logic (ISMVL'05)

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This paper proposes a design for signed-digit CMOS (SD-CMOS) basic circuits, such as a driver circuit, an inverter circuit, and a full-adder circuit, and describes a parallel multiplier circuit capable of high-speed operation with a time of about 10 nsec independent of the bit length. The proposed CMOS basic circuits utilize a multi-voltage power supply to enable dynamic operation with pre-charged output terminals at signal level 0 (VDD1). This design methodology is applicable to arithmetic circuits for highly accurate, high-speed processors.

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“…Most digital multiplier designs are based on the Normal Binary (NB) number representation [7,[20][21][22][23][24][25][26][27][28]. For signed number, a widely accepted interpretation of this term is the two's complement representation of the number.…”

Section: Motivationmentioning

confidence: 99%

Design and analysis of redundant binary booth multipliers

He¹

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First and foremost, I am deeply indebted to my supervisor, Associate Professor Chang Chip Hong, for all of his invaluable guidance, continuous technical and personal support during my PhD candidature at Nanyang Technological University. His many years of research experience and unique sense in engineering research have led to a very effective and insightful guidance to my research work. In particular, I wish to thank him for teaching me the philosophies of research and intangible skills, which are the most important knowledge I have acquired in this research program. What I have learned from him will benefit me well beyond my graduation in my future career and personal life. Special thanks to Mrs. Chang for her continuous concern and kindness, from which I gained lots of wonderful memories. I really treasure the time spent with them. I would like to thank Dr. Gu Jiangmin and Dr. Hossam A. H. Fahmy for their valuable discussions, suggestions and support in the research work. I would also like to thank the fellow members from the Chip's Family for the long run friendship, and invaluable help pertaining to my research. To the staffs and other students in the Center for Integrated Circuits and Systems (CICS) and the Center for High Performance Embedded Systems (CHiPES), I wish to convey my appreciation to all of them for their kind and friendly i ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library ii assistance. ACKNOWLEDGEMENTS I would also like to express my gratitude to my previous supervisors and colleagues in the Institute of Microelectronics (IME). I would not have been here in Singapore if Dr. Xue Ping had not recruited me as a digital Ie designer in 2001. I would like to thank Ms. Doreen Yeo Lee Guek and Mr. Wang Zhongjun particularly for their guidance in the early stage of my career. I am grateful to my fiance Li Qiang for his devotion, understanding, and patience. I would never know whether I am able to go through the tough time without his support. He is the most important source of inspiration, encouragement, and happiness. My parents are always there for me and always have faith in me. It is never enough to say thanks to them. I dedicate this thesis to my parents with all my love.

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A 2.7 ns 0.25 μm CMOS 54×54 b multiplier

Cited by 5 publications

References 5 publications

A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry

A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry

Signed-digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation

Design and analysis of redundant binary booth multipliers

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