A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry

Mochizuki, Ayako; Hanyu, Takahiro

doi:10.1109/vlsic.2005.1469382

Cited by 11 publications

(3 citation statements)

References 5 publications

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“…Originally, the multi-valued logic (MVL) technology was developed to economize the circuit structure by using compact computing elements [16], or to enhance memory capacity by storing more bits in a single memory cell [14]. Although a pure MVL system is still a topic of research, the concept of MVL has been successfully applied to baseband digital data communication and storage.…”

Section: Multi-level Logic Test Applicationmentioning

confidence: 99%

Adopting multi-valued logic for reduced pin-count testing

Zhang

Agrawal

2015

2015 16th Latin-American Test Symposium (LATS)

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The reduced pin-count test (RPCT) has been proposed for testing cost reduction in various scenarios like scan, test compression and multi-site test. In this paper, we propose a new RPCT technique in which several digital signals are combined into a single multi-valued logic (MVL) signal. Mixed-signal components, digital-to-analog and analogto-digital converters, are used to compress the tester channels and then to expand the test at the circuit under test. The method allows greater bandwidth efficiency than the existing SerDes alternative. However, the MVL signal can be sensitive to noise and nonlinearity errors. To ensure the reliability of test application, we provide an error control scheme. The paper gives theoretical analysis as well as experimental evidence.

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Section: Multi-level Logic Test Applicationmentioning

confidence: 99%

Adopting multi-valued logic for reduced pin-count testing

Zhang

Agrawal

2015

2015 16th Latin-American Test Symposium (LATS)

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“…This point is rather critical in system-on-chip applications. Consider the 54x54 bit fast multiplier circuit based on radix-2 signed-digit arithmetic (Mochizuki, 2005). This CMVL circuit consumes more than 70mW with 500MHz operation frequency and it would be difficult to integrate hundreds of these multipliers in a single chip.…”

Section: Comparison Of Speed and Power Dissipationmentioning

confidence: 99%

Arithmetic Circuits Realized by Transferring Single Electrons

Zhang¹,

Wu²

2010

Cutting Edge Nanotechnology

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“…To reduce the overhead of the asynchronous operation, high-speed and wireefficient asynchronous communication links based on onephase signalling have been reported [9], [10]. In these links, the number of wires and communication steps are reduced to those in a synchronous communication link by utilizing multiple-valued encoding and multiple-valued currentmode (MVCM) circuits [11], [12]. However, variation effects, such as process, supply-voltage and temperature variations, have not been considered in the MVCM circuits, while in binary-CMOS circuits, the variation effects and their reduction techniques have been reported [13]- [15].…”

Section: Introductionmentioning

confidence: 99%

Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link

Onizawa

Hanyu

2010

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents highly reliable multiple-valued onephase signalling for an asynchronous on-chip communication link under process, supply-voltage and temperature variations. New multiple-valued dual-rail encoding, where each code is represented by the minimum set of three values, makes it possible to perform asynchronous communication between modules with just two wires. Since an appropriate current level is individually assigned to the logic value, a sufficient dynamic range between adjacent current signals can be maintained in the proposed multiple-valued current-mode (MVCM) circuit, which improves the robustness against the process variation. Moreover, as the supply-voltage and the temperature variations in smaller dimensions of circuit elements are dominated as the common-mode variation, a local reference voltage signal according to the variations can be adaptively generated to compensate characteristic change of the MVCM-circuit component. As a result, the proposed asynchronous on-chip communication link is correctly operated in the operation range from 1.1 V to 1.4 V of the supply voltage and that from −50 • C to 75 • C under the process variation of 3σ. In fact, it is demonstrated by HSPICE simulation in a 0.13-μm CMOS process that the throughput of the proposed circuit is enhanced to 435% in comparison with that of the conventional 4-phase asynchronous communication circuit under a comparable energy dissipation.

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A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry

Cited by 11 publications

References 5 publications

Adopting multi-valued logic for reduced pin-count testing

Adopting multi-valued logic for reduced pin-count testing

Arithmetic Circuits Realized by Transferring Single Electrons

Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link

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