A 2-D Multiple Transform Processor for the Versatile Video Coding Standard

Garrido, M.J.; Pescador, F.; Chavarrías, Miguel; Lobo, Pedro J.; Sanz, C.

doi:10.1109/tce.2019.2913327

Cited by 36 publications

(30 citation statements)

References 10 publications

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“…Work in [25] involves 5 transform types but is restricted to only 4×4 and 8×8 block sizes reaching 30 fps for 4K video coding. Work in [27] presents also an interesting 2D implementation of MTS module regarding hardware cost. It is unified for all block sizes from 4×4 to 32×32 but is not able to support real time coding for 4K videos.…”

Section: Synthesis Results and Discussionmentioning

confidence: 99%

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Forward-Inverse 2D Hardware Implementation of Approximate Transform Core for the VVC Standard

Kammoun

Hamidouche

Philippe

et al. 2020

IEEE Trans. Circuits Syst. Video Technol.

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The future video coding standard named Versatile Video Coding (VVC) is expected by the end of 2020. VVC will enable better coding efficiency than the current High Efficiency Video Coding (HEVC) standard. This coding gain is brought by several coding tools. The Multiple Transform Selection (MTS) is one of the key coding tools that have been introduced in VVC. The MTS concept relies on three transform types including Discrete Cosine Transform (DCT)-II, Discrete Sine Transform (DST)-VII and DCT-VIII. Unlike the DCT-II that has fast computing algorithms, the DST-VII and DCT-VIII rely on more complex matrix multiplication. In this paper an approximation approach is proposed to reduce the computational cost of the DST-VII and DCT-VIII. The approximation consists in applying adjustment stages, based on sparse block-band matrices, to a variant of DCT-II family mainly DCT-II and its inverse. Genetic algorithm is used to derive the optimal coefficients of the adjustment matrices. Moreover, an efficient hardware implementation of the forward and inverse approximate transform module is proposed. The architecture design includes a pipelined and reconfigurable forward-inverse DCT-II core transform as it is the main core for DST-VII and DCT-VIII computations. The proposed 32-point 1D architecture including low cost adjustment stages allows the processing of a video in 2K and 4K resolutions at 1095 and 273 frames per second, respectively. A unified 2D implementation of forwardinverse DCT-II, approximate DST-VII and DCT-VIII is also presented. The synthesis results show that the design is able to sustain a video in 2K and 4K resolutions at 386 and 96 frames per second, respectively, while using only 12% of Alms, 22% of registers and 30% of DSP blocks of the Arria10 SoC platform.

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Section: Synthesis Results and Discussionmentioning

confidence: 99%

“…Moreover, this design does not consider asymmetric block size combinations. This work has been then extended in [27] to support 2D design using Dual port RAMs for the transpose memory. They proposed to pipeline the 2D process placing two separate 1D processors in parallel for horizontal and vertical transforms.…”

Section: A Multiple Transform Selection In Vvcmentioning

confidence: 99%

Forward-Inverse 2D Hardware Implementation of Approximate Transform Core for the VVC Standard

Kammoun

Hamidouche

Philippe

et al. 2020

IEEE Trans. Circuits Syst. Video Technol.

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“…Most studies focus on earlier version of VVC, and there are few ASIC-based designs for the VVC MTS. For comparison, Table 3 lists the key performance of state-of-the-art ASIC and FPGA-based works, including the VVC-MTS related works [11,9,6,10]. Gate count is the logical calculation part and it can be seen from Table 3 that compared with implementations of Fan et al [11] and Mert et al [6], our solution has obvious advantages.…”

Section: Resultsmentioning

confidence: 99%

“…The design relies on two 1D implementations connected with a transpose memory. Garrido et al in [9] extended their work to support a 2D transform. The synthesis results targeting multiple state of the art Field-Programmable Gate Array (FPGAs) platforms show that the design can support in the best scenario 4K video resolution at 23 frames per second.…”

Section: Existing Hardware Implementationsmentioning

confidence: 99%

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Lightweight Hardware Implementation of VVC Transform Block for ASIC Decoder

Farhat

Hamidouche

Grill

et al. 2020

ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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Versatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. Compared to its predecessor, VVC introduces new coding tools to make compression more efficient at the expense of higher computational complexity. This rises a need to design an efficient and optimised implementation especially for embedded platforms with limited memory and logic resources. One of the newly introduced tools in VVC is the Multiple Transform Selection (MTS). This latter involves three Discrete Cosine Transform (DCT)/Discrete Sine Transform (DST) types with larger and rectangular transform blocks. In this paper, an efficient hardware implementation of all DCT/DST transform types and sizes is proposed. The proposed design uses 32 multipliers in a pipelined architecture which targets an ASIC platform. It consists in a multi-standard architecture that supports the transform block of recent MPEG standards including AVC, HEVC and VVC. The architecture is optimized and removes unnecessary complexities found in other proposed architectures by using regular multipliers instead of multiple constant multipliers. The synthesized results show that the proposed method which sustain a constant throughput of two pixels/cycle and constant latency for all block sizes can reach an operational frequency of 600 Mhz enabling to decode in real-time 4K videos at 48 fps.

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