A 2 Gb/s 21 CH low-latency transceiver circuit for inter-processor communication

Tanahashi, Toshio; Kurisu, M.; Yamaguchi, H.; Nedachi, Takaaki; Arai, M.; Tomari, S.; Matsuzaki, Takanori; Nakamura, Kazuyuki; Fukaishi, M.; Naramoto, S.; Sato, Takahiro

doi:10.1109/isscc.2001.912545

Cited by 10 publications

(1 citation statement)

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“…The transmission channel, such as an FR4 PCB trace, has limited bandwidth and hence signaling at 3.125Ghis invariably creates enough inter-symbol interference (HI) to effectively close the eye pattern at the receiver end making conventional receivers useless for data recovery. Transmitter pre-emphasis equalization was sometimes used to pre-distort the transmitted data for channel compensation [2]. Receiver Decision Feedback-based Equalization (DFE) was also used to open the receiver eye-diagram further [3].…”

Section: Introductionmentioning

confidence: 99%

A quad multi-speed serializer/deserializer with analog adaptive equalization

Wang

Jiang

Tam

et al.

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

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A quad multi-speed (1.25/1.5625/2.5/3.125Gbis) serializer ideserializer implemented in 0.25um CMOS technology is described. It uses a 4x interleaved sample-and-hold receiver architecture. An analog adaptive receiver equalizer and a linear phase detector are used for clock and data recovery. At 3.125Gh/s, the serializer RMS jitter is 2 . 4~s . The serializer ideserializer runs error free for Z3'-1 PRBS data pattern over various length, up to 40-inches, of FR4 PCB trace.

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Section: Introductionmentioning

confidence: 99%