A 2-GHz quadrature hybrid implemented in CMOS technology

Frye, R.C.; Kapur, Sharad; Melville, Robert

doi:10.1109/jssc.2002.808287

Cited by 124 publications

(46 citation statements)

References 8 publications

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“…The designed coupler is categorized as a hybrid-coupled line coupler, and the transformer-based inductive coupling is incorporated in this design [15]. With regard to the quality factor, it is mainly affected by metal line resistance and both capacitive and magnetic coupling to the substrate [16].…”

Section: A Ipd Quadrature Couplermentioning

confidence: 99%

A Triple-Mode Balanced Linear CMOS Power Amplifier Using a Switched-Quadrature Coupler

Jeon

Park

Huang

et al. 2012

IEEE J. Solid-State Circuits

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A triple-mode class-AB balanced linear power amplifier (PA) is realized in standard 0.18-m CMOS technology. For the average efficiency enhancement, the triple-mode operation realizes a switched-quadrature coupler with a balanced topology to achieve robust load insensitivity. The PA and RF switches uniquely utilize the isolation port of the switched-quadrature coupler as a signal path in a low-power (LP) mode of operation, and the incorporated output matching network satisfies the condition from the quadrature coupler in the LP mode while providing the necessary load-pull impedance from the PA output side in the high-power (HP) mode. To obtain low loss and high quality factor ( ) of the passive output-combining network, a transformer-based quadrature coupler is implemented using a silicon-based integrated passive device process. With a 3.4-V power supply, the PA transmits a maximum output power of 28.4 dBm with 40.7% of power-added efficiency (PAE) and linear output power up to 26.6 dBm with 35% of the PAE using a 3-GPP WCDMA modulated signal. With the triple-mode operation, a PAE at 16 dBm is enhanced from 11.1% to 17%, and 47 mA of quiescent current is saved. The PA also shows robust operation under 2.5:1 of VSWR condition, achieving 1 dB of the gain variation and less than 3.9 dB of ACLR variation. This work demonstrates the potential of a highly efficient CMOS PA for WCDMA applications.Index Terms-Balanced topology, cascode, CMOS, integrated passive device (IPD), load immunity, multi-mode, power amplifier (PA), quadrature coupler, RF switches, WCDMA.

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Section: A Ipd Quadrature Couplermentioning

confidence: 99%

A Triple-Mode Balanced Linear CMOS Power Amplifier Using a Switched-Quadrature Coupler

Jeon

Park

Huang

et al. 2012

IEEE J. Solid-State Circuits

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“…First, a 3D EM simulator is used to obtain the S-Parameters of the conventional LC. Then these S-Parameters are exported to a circuit simulator (Agilent ADS) as the S-Parameters of an inductively coupled coupler, for which the EQ model proposed by Frye et al [35] is shown in Figure 3a. The even mode and odd mode analysis is performed on the EQ to obtain the odd and even mode impedances using eqs.…”

Section: Cdos Embedded Lc Design Proceduresmentioning

confidence: 99%

Design of lange coupler for MIC and MMIC technology using complementary deformed omega structure

Mishra¹,

Kumar

Mishra

et al. 2011

Int J RF and Microwave Comp Aid Eng

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A novel design for a 3 dB Lange coupler based on complementary deformed omega structure (CDOS) is proposed. Observations, from parametric study for the CDOS based Lange coupler, are provided to aid in the design process. A functional linked artificial neural network has been used to determine the dimensions of the CDOS. Electromagnetic simulations have been validated with experimental results obtained from fabricated prototypes. V C 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE 22:85-92, 2012.

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“…The 94-GHz CMOS phase shifter consumes 43 mW, of which 20 mW are in the rotator, from 1.2 V supply. The 77-GHz SiGe BiCMOS phase-shifter utilizes a singleended, transformer-based, quadrature hybrid [4] illustrated in Fig. 6 which is a modified version of the one depicted in Fig.…”

Section: Phase Shifter Topologymentioning

confidence: 99%

W-band 65-nm CMOS and SiGe BiCMOS transmitter and receiver with lumped I-Q phase shifters

Sarkas

Khanpour

Tomkins

et al. 2009

2009 IEEE Radio Frequency Integrated Circuits Symposium

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This paper describes 80-94 GHz and 70-77 GHz I-Q phase shifters and the corresponding transmitter and receiver ICs, fabricated in 65-nm CMOS and SiGe BiCMOS technologies, respectively. Lumped inductors and transformers are employed to realize small-form factor 90 • hybrids as needed in high density phased arrays. The CMOS transmitter operates with a saturated output power of +3 dBm and exhibits maximum absolute phase and amplitude errors of 14 • and 5.5 dB, respectively, when the phase is varied from 0 • to 360 • in steps of 22.5 • . The absolute phase error in the SiGe BiCMOS receiver is less than 8 • , with a maximum gain imbalance below 3 dB over its 3-dB bandwidth of 70-77 GHz. The peak gain and power consumption are 3.8 dB and 142 mW from 1.2 V supply for the CMOS transmitter, and 17 dB and 128 mW from 1.5 V and 2.5 V supplies for the SiGe BiCMOS receiver.Index Terms-mm-wave phase shifter, phase interpolation, CMOS weighted adder, BiCMOS variable gain amplifier.

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A 2-GHz quadrature hybrid implemented in CMOS technology

Cited by 124 publications

References 8 publications

A Triple-Mode Balanced Linear CMOS Power Amplifier Using a Switched-Quadrature Coupler

A Triple-Mode Balanced Linear CMOS Power Amplifier Using a Switched-Quadrature Coupler

Design of lange coupler for MIC and MMIC technology using complementary deformed omega structure

W-band 65-nm CMOS and SiGe BiCMOS transmitter and receiver with lumped I-Q phase shifters

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