A Triple-Mode Balanced Linear CMOS Power Amplifier Using a Switched-Quadrature Coupler

Abstract

A triple-mode class-AB balanced linear power amplifier (PA) is realized in standard 0.18-m CMOS technology. For the average efficiency enhancement, the triple-mode operation realizes a switched-quadrature coupler with a balanced topology to achieve robust load insensitivity. The PA and RF switches uniquely utilize the isolation port of the switched-quadrature coupler as a signal path in a low-power (LP) mode of operation, and the incorporated output matching network satisfies the condition from the quadrature coupler in the LP mode while providing the necessary load-pull impedance from the PA output side in the high-power (HP) mode. To obtain low loss and high quality factor ( ) of the passive output-combining network, a transformer-based quadrature coupler is implemented using a silicon-based integrated passive device process. With a 3.4-V power supply, the PA transmits a maximum output power of 28.4 dBm with 40.7% of power-added efficiency (PAE) and linear output power up to 26.6 dBm with 35% of the PAE using a 3-GPP WCDMA modulated signal. With the triple-mode operation, a PAE at 16 dBm is enhanced from 11.1% to 17%, and 47 mA of quiescent current is saved. The PA also shows robust operation under 2.5:1 of VSWR condition, achieving 1 dB of the gain variation and less than 3.9 dB of ACLR variation. This work demonstrates the potential of a highly efficient CMOS PA for WCDMA applications.Index Terms-Balanced topology, cascode, CMOS, integrated passive device (IPD), load immunity, multi-mode, power amplifier (PA), quadrature coupler, RF switches, WCDMA.

Stacking the Deck for Efficiency: RF- to Millimeter-Wave Stacked CMOS SOI Power Amplifiers

“…Implementing wide-band large-signal CMOS amplifiers has been accomplished using multiple techniques including distributed amplifiers (DAs) [38], balanced amplifiers [39], inverter-based class-D PAs [40], and designs based on a high-order output-matching network [41]. DAs implemented on Si substrate are often characterized by large area, low output power, and inefficient performance due to the small voltage swing across the CS or cascode devices used in the design and the lossy transmission lines available in CMOS technology.…”

“…In such cases, the extension of the bandwidth may be achieved by dividing the input power in two paths, each amplifying in a portion of the bandwidth, and then combining them at the output. The balanced amplifier is a typical example of such method [39].…”

A Highly Efficient Dual-Mode 3G/4G Linear CMOS Stacked-FET Power Amplifier Using Active-Bypass

“…To enhance the efficiency in the low output power (Pout) level, several methods have been proposed [1][2][3][4]. Among these, an active stage-bypass technique is an attractive solution, because it can significantly reduce the average current consumption of a PA.…”

“…Among these, an active stage-bypass technique is an attractive solution, because it can significantly reduce the average current consumption of a PA. This technique is subdivided into a conventional stagebypass [3,4] and an active full-bypass [2], which utilize a driver-stage and a separate bypass-stage, respectively. To achieve extremely low quiescent current (3-5 mA) and higher efficiency at backed-off Pout of more than 15 dB, the active full-bypass method is preferred.…”

“…Recent CMOS technology has also played an important role in handset PA design due to its size and cost benefits. By employing several power combining techniques such as the differential cascode and stacked-FET structures, the breakdown issue of a CMOS device is avoided and thus CMOS PAs are able to deliver watt-level Pout [3][4][5][6][7]. For these reasons, a multimode watt-level linear CMOS PA covering broad signal bandwidth is demanded.…”