Stacking the Deck for Efficiency: RF- to Millimeter-Wave Stacked CMOS SOI Power Amplifiers

Abstract

T he emerging demand for high-capacity wireless mobile communication and the advent of the Internet of Things and fifthgeneration communication standards have motivated the development of high-performance transceivers. The power amplifier (PA) is the most critical part in the transmit path and dominates the transceiver's performance, including coverage range, data rate, spectrum compliance, and dc power dissipation. Integration capability and the relatively low cost of complementary-metal-oxide-semiconductor (CMOS) technology, on the other hand, have propelled it into the wireless market. CMOS technology enables complete system-on-chip solutions, resulting in ), Yingheng Tang (tang96@purdue.edu), and Saeed Mohammadi (saeedm@purdue.edu) are with the Birck Nanotechnology Center, Purdue University West Lafayette, Indiana, United States.im ag e lic en se d by in gr am pu bl is hi ng

Design of Stacked-MOS Transistor mm-Wave Class C Amplifiers for Doherty Power Amplifiers

“…The higher bandwidth and data rate offered by millimeter wave (mm-wave) spectrum has attracted the attention of industries and academic research units in order to work out the viability of implementing the next generation of high data rate systems such as 5G, IoT, etc. [1]- [3].…”

“…Nonetheless, low breakdown level of scaled CMOS transistors yields limited obtainable amount of power from a single transistor. In order to overcome the mentioned problem, stacking transistors in series connection on top of each other was proposed [1]- [3], [7]- [9].…”

Design of Multi-Stacked CMOS mm-Wave Power Amplifiers for Phased Array Applications Using Triple-Well Process

“…Stacking transistors ( Fig. 1) were proposed to overcome the issues such as low breakdown level, low output impedance, large parasitics, and low output power provided by a single transistor, when CMOS transistors are utilized as mm-wave power amplifiers (PA) for the next generation of wireless communications systems [1] - [9]. A typical schematic of stacked CMOS PA topology is shown in Fig.…”

Performance Improvement of Multi-Stacked CMOS mm-Wave Power Amplifiers Based on Negative Capacitance Phase Compensation

“…However, low breakdown level of scaled CMOS transistors yields limited obtainable amount of power from a single transistor. To overcome the issue, stacking transistors was proposed, [1]- [4]. Due to the presence of transistor parasitics, though, stacking topology requires additional networks for inter-stage matching and phase alignment of each and every amplifier stage in order for the signals to be efficiently superimposed up to the output node [5]- [8].…”