A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs

Abstract

In this letter, a fully integrated 20-dBm RF power amplifier (PA) is presented using 0.25-m-gate silicon-on-sapphire metal-oxide-semiconductor field-effect transistors (MOSFETs). To overcome the low breakdown voltage limit of MOSFETs, a stacked FET structure is employed, where transistors are connected in series so that each output voltage swing is added in phase. By using triple-stacked FETs, the optimum load impedance for a 20-dBm PA increases to 50 , which is nine times higher than that of parallel FET topology for the same output power. Measurement of a single-stage linear PA shows small-signal gain of 17.1 dB and saturated output power of 21.0 dBm with power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access modulated signal, the PA shows an average output power of 16.3 dBm and PAE of 18.7% with adjacent channel power ratio below 42 dBc. Index Terms-Metal-oxide-semiconductor field-effect transistor (MOSFET), power amplifier (PA), silicon-on-sapphire (SOS), stacked transistors.

High-Efficiency Microwave and mm-Wave Stacked Cell CMOS SOI Power Amplifiers

“…To obtain high power, it is essential to achieve uniform drain-source voltage swing contribution from each transistor within the cell with minimum phase differences. The capacitors at the gate of CG stages calculated from (9) and (10) are further optimized to achieve uniform voltage swings across each transistor, as confirmed by simulation, leading to capacitor values of C c = C 1 = 800 fF and C 2 = 230 fF (a g m R L = 5 is estimated) [25]. Fig.…”

“…Both PAs are designed based on triple Casecode cells with a bottom feed configuration. The first PA is designed for K-band/5G applications (20)(21)(22)(23)(24)(25)(26)(27)(28)(29)(30), while the second PA is targeted at U-band (45-55 GHz) frequencies for ultrahigh-bandwidth communications. The CMOS SOI technology surrounds each transistor with buried and trench oxide, leading to electrically isolated transistors.…”

CMOS Integrated Switched-Mode Transmitters for Wireless Communication

“…As limited supply voltage is one of the major challenges in CMOS PA design, other strategies have been used to effectively add the output voltages, such as using a transformer to combine output power (Aoki et al, 2008;Haldi et al, 2008) or stacking devices, making sure that the voltage over each device stays below the maximum (Stauth & Sanders, 2008;Jeong et al, 2006). However, generally this slightly impairs the efficiency, counteracting the intended advantage of a higher supply voltage.…”

Design of Power Amplifiers Using Stacked Topology

“…The gain design is tabulated in Table 1, using the model given in [3]. This capacitor termination is the most crucial step in obtaining high output power by maximizing the voltage and current swings under large signal operation [4][5][6].…”