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Design and implementation of high-efficiency microwave and mm-wave CMOS silicon-on-insulator (SOI) power amplifiers (PAs) based on a stacked cell approach is presented. Two stacked cell PAs have been implemented in GlobalFoundries 45-nm CMOS SOI technology. The first PA operating at K-band (24-28 GHz) is designed with three stacked triple Cascode cells. Each cell uses three standard transistors with separate layout. At 24 GHz, the K-band PA biased under a supply voltage of 10.8 V measures a maximum linear power gain of 13 dB, a saturated output power P SAT of 25.3 dBm, a −1-dB output power P 1dB of 23.8 dBm, and a peak poweradded efficiency (PAE) of 20%. The second PA targeted at U-band frequencies is designed with two stacked triple Cascode cells. Transistors in each cell have a combined layout that reduces parasitic capacitances, leading to significant improvement in the PAE at mm-wave frequencies. The U-band PA operates from 42 to 54 GHz. At 46 GHz, and under a supply voltage of 6 V, it measures a saturated output power ( P SAT ) of 22.4 dBm, a linear gain of 17.4 dB, and an unprecedented peak PAE of 42%.Index Terms-CMOS, fifth-generation (5G), high efficiency, microwave frequency, millimeter-wave (mm-wave) frequency, power amplifier (PA), silicon-on-insulator (SOI), stacked transistors.

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