A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS

Abstract

In this paper, a wideband low-noise amplifier (LNA) with a two-fold noise cancellation scheme is proposed. Finetuned for advanced CMOS, the proposed LNA architecture uses a common-gate input branch to provide wideband input matching. It is followed by two stages of the common-source structure which cancels the noise and distortion of the first and second stages and relaxes the design restriction on the first noise-cancellation stage. The provided circuit-level analysis is verified by simulations. The proposed LNA is fabricated in 28-nm CMOS. It achieves a minimum noise figure (NF) of 2.5 dB and input return loss (S 11 ) < −15 dB over 0.02-2 GHz bandwidth while consuming only 4.1 mW from a 1 V supply and driving an external 50-load. The −3 dB power gain (S 21 ) is 18.5 dB and IIP3 is +4.25 dBm.

A wideband CMOS LNA using noise‐canceling topology and gm‐boosting technique

“…Table 1 shows a comparison of this work with prior works. [4][5][6][7][8][9][10][11][12][13] Although the linearity shown in Im et al 7 is better than the proposed LNA, it has a great problem of DC power consumption. In addition, this work achieves higher gain and flatter NF than the work reported in Im et al 7 Compared with Liu et al 4 and Kumar et al, 8 the proposed LNA exhibits a higher maximum gain, flatter NF, lower supply voltage, and smaller circuit size.…”

“…Table 1 shows a comparison of this work with prior works 4–13 . Although the linearity shown in Im et al 7 is better than the proposed LNA, it has a great problem of DC power consumption.…”

Design of High-IF Discrete-Time Receivers for IoT: Demystifying Aliasing Trade-Offs

“…A typical DT-RX front-end would include a low-noise transconductance amplifier (LNTA), see Fig. 4, to provide a current input for the mixer [34]. The mixer's sampling process includes an inherent WIS filtering effect.…”

A 0.7-2.7 GHz Low Power LNA with Noise Cancellation and Current-Reused Technique

“…In addition, by using the sweet spot technique [19][20], it is possible to reduce the non-linearity effect of M 1 and M 2 transistors, which have a greater contribution in the linearity of the LNA. According to Eq.18, if the values of the first and second derivatives of g m can be reduced, the non-linearity effect caused by the transistor would be reduced.…”