A 200MHz 0.65fJ/(Bit·Search)1.152kb pipeline content addressable memory in 28nm CMOS

Fary, F.; Mangiagalli, L.; Pipino, A.; Resta, Federica; Matteis, M. De; Basçhirotto, A.

doi:10.1109/prime.2017.7974180

Cited by 3 publications

(4 citation statements)

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“…For a legitimate comparison of the performance with the proposed design implementation, energy and delay of the referred designs are normalized using Equations ( 5) and ( 6) as presented in [4]. Reference 2016 [1] 2018 [9] 2018 [15] 2018 [20] 2019 [21] 2020 [22] 2019 [23] 2016 [25] 2017 [26]…”

Section: Performance Comparison Summarymentioning

confidence: 99%

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Match‐line control unit for power and delay reduction in hybrid CAM

Hussain

Mahendra²,

Mishra

et al. 2021

IET Circuits, Devices & Syst

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Content addressable memory (CAM) is a hardware search engine utilised for accelerating translation and table look‐up in network routers and data processing systems. This article proposes a NAND‐NOR match‐line (ML) based CAM architecture with the main goals of elevating search performance and energy efficiency. A competent ML control unit (MLCU) is introduced to provide a short discharge path for output match‐line after processing the ML sections. In this architecture, tag mismatch based on memory traces is utilised (in NAND‐MLs) to deactivate redundant NOR‐MLs in an attempt to reduce the overall ML switching activity. Based on the decision of NAND‐ML partition, the MLCU restores the charge to reduce ML glitches during the evaluation phase. Match‐line delay of the proposed 64×32‐bit hybrid CAM is 366.90 ps in a standard 45‐nm technology at 1 V, which is 56.51% and 72.55% reductions compared to a conventional CAM and a segmented CAM, respectively. Reduction in precharge power and search power of the presented CAM leads to 6× enhancements of power‐delay‐product from existing hybrid CAMs. The proposed CAM can operate up to low supply voltages by dissipating only 0.10 fJ/bit/search at 0.5 V.

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Section: Performance Comparison Summarymentioning

confidence: 99%

“…CAM cells based on adiabatic logic scheme allow energy recovery in order to improve energy efficiency [24]. Cascaded CAM design with OR-type cells [25] and pipeline CAM with NOR-ML [26] employ mismatch filtering to eliminate redundant ML discharges but cost huge delay due to sequential searching across several ML stages.…”

Section: Introductionmentioning

confidence: 99%

Match‐line control unit for power and delay reduction in hybrid CAM

Hussain

Mahendra²,

Mishra

et al. 2021

IET Circuits, Devices & Syst

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“…Content Addressable Memories (CAMs), also known as Associative Memories (AM), are very popular digital devices used for data storage and data processing applications. They are exploited, for example, as look up tables for IP addresses in network routers and find applications as well in data compression algorithms, database management, and image pattern recognition processing [1][2][3][4][5]. In recent years, they have also been exploited in Artificial Neural Networks [6,7] and hyperdimensional computing for Artificial Intelligence (AI) [8], where highly efficient associative memories tend to be a common specification.…”

Section: Introductionmentioning

confidence: 99%

“…However, this architecture might lead to an increase in power consumption, due to the contemporary and continuous comparison activity in every device cell [3]. For this reason, different hardware solutions, based on particular single-bit cells [3][4][5][9][10][11] or various power saving algorithms [11][12][13], have been explored in the past.…”

Section: Introductionmentioning

confidence: 99%

A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments

Fary

Basçhirotto

2020

JLPEA

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This paper presents a transistor-level design with extensive experimental validation of a Content Addressable Memory (CAM), based on an eXclusive OR (XOR) single-bit cell. This design exploits a dedicated architecture and a fully custom approach (both in the schematic and the layout phase), in order to achieve very low-power and high-speed performances. The proposed architecture does not require an internal clock or pre-charge phase, which usually increase the power request and slow down data searches. On the other hand, the dedicated solutions are exploited in order to minimize parasitic layout-induced capacitances in the single-bit cell, further reducing the power consumption. The prototype device, named CAM-28CB, is integrated in the deeply downscaled 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) Bulk (28CB) technology. In this way, the high transistor transition frequency and the intrinsic lower parasitic capacitances allow the system speed to be improved. Furthermore, the high radiation hardness of this technology node (up to 1Grad TID), together with the CAM-28CB high-speed and low-power performances, makes this device suitable for High-Energy Physics experiments, such as ATLAS (A Toroidal LHC ApparatuS) at Large Hadron Collider (LHC). The prototype operates at a frequency of up to 100 MHz and consumes 46.86 µW. The total area occupancy is 1702 µm2 for 1.152 kb memory bit cells. The device operates with a single supply voltage of 1 V and achieves 0.41 fJ/bit/search Figure-of-Merit.

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