An efficient algorithm for a link budget definition of a Bluetooth Low Energy (BLE) receiver is presented. The aim of this paper is to provide a simple procedure that the analog designers can use for a preliminary but reliable definition of the BLE RX building blocks specs. Starting from the BLE standard, the global specifications of the analog front-end are derived (noise figure, IIP3, IIP2, etc.) and, in a second phase, distributed among the building blocks. Finally the system design is validated through simulation results obtained from a Simulink analysis.Keywords-RF front-end, analog base-band, link budget, RX architecture, NF, IIP3, IIP2, Bluetooth Low Energy.I.

A B S T R A C TWe present the prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for high-luminosity LHC operation. This ASIC is based on a previously submitted demonstrator ASIC designed for timing performance evaluation, and includes all features necessary for the various operation modes, as well as the migration to the TSMC 130 nm CMOS technology. We present the TDC design with the emphasis on added features and performance optimization. Tests of the timing performance demonstrate that this ASIC meets the design specifications. The TDC has a bin size of about 780 ps, and a timing bin variations within ±40 ps for all 24 channels with leading and trailing edge digitization, while the power consumption has been limited to 250 mW, corresponding to a consumption of about 5.2 mW per edge measurement..

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This paper presents a Fast-Tracker front-end (FTfe) for ATLAS small-diameter Muon Drift Tube (sMDT) detectors of the Phase-II Upgrade HL-LHC. This design addresses the higher rate capability required by sMDT and reduces the dead-time below the maximum drift time, further increasing the efficiency. The front-end ensures a fast baseline restoration with a reset interval of maximum 160 ns, so that the secondary spurious pulses are avoided and the successive muon signals can be detected soon and correctly. The device has been designed in 1V-28nm-CMOS technology; 4.7mV/fC sensitivity and 0.24fC ENC are achieved with a core area of 0.03mm 2 .