A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications

Tian, Jing; Lin, Jun; Wang, Zhongfeng

doi:10.1109/tcsii.2017.2706273

Cited by 9 publications

(6 citation statements)

References 21 publications

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“…However, polar decoders can achieve a peak throughput performance of 25.6 Gbps by unrolling and pipelining large amounts of data blocks [46]. The parallelization degree is higher for LDPC decoders, which allows throughput performance to increase up to 172.4 Gbps for binary decoders [47] and 21.6 Gbps for non-binary decoders [48].…”

Section: Overview Of Surveys On Eccsmentioning

confidence: 99%

“…Furthermore, works that do not report SNR and the number of iterations [78], [116], [122]- [124], [133] or employ early termination [48], [67], [80], [94], [111], [114], [117], [119], [121], [126] cannot be compared against other decoders since the SNR impacts the throughput performance and little can be inferred from the number of iterations.…”

Section: ) Analysismentioning

confidence: 99%

“…The designs using ISRB [120], IHRB [121] and WBRB [48] achieve excellent performance and can be alternatives to better-known algorithms such as MM and EMS. In this figure, we can see that data points can be clustered in process node technologies.…”

Section: Asicmentioning

confidence: 99%

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A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

Ferraz

Subramaniyan

Ramesh

et al. 2022

IEEE Commun. Surv. Tutorials

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Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting performance than binary low-density parity-check (LDPC) codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized NB-LDPC decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing NB-LDPC decoding hardware that targets the optimization of these parameters. Even though existing NB-LDPC decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on application-specific integrated-circuit (ASIC), field-programmable gate array (FPGA) and Manuscript

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Section: Overview Of Surveys On Eccsmentioning

confidence: 99%

Section: ) Analysismentioning

confidence: 99%

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A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

Ferraz

Subramaniyan

Ramesh

et al. 2022

IEEE Commun. Surv. Tutorials

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“…Implementing LDPC codes, especially QC-LDPC codes onto FPGAs or application-specific integrated circuits (ASICs), are very common today. Comprehensive studies [11]- [13] have been conducted to reduce the complexity and improve the accuracy and throughput of the QC-LDPC decoders, such as applying appropriate calculations [14]- [17] and different structures of LDPC codes [18]- [20]. All the aforementioned studies adopt FPGAs or ASICs as their testing platforms in order to parallel and pipeline their decoding algorithm to the best extent.…”

Section: Related Workmentioning

confidence: 99%

An Effective Multi-Mode Iris Authentication System on a Microprocessor-FPGA Heterogeneous Platform With QC-LDPC Codes

Sham

et al. 2021

IEEE Access

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With the emergence and popularity of iris biometrics, there are increasing concerns regarding the feasibility of iris authentication systems and their corresponding variability reduction methods. The former issues are typically addressed by optimizing key factors, such as iris size, image quality and acquisition wavelength. As for the latter, introducing error correction codes to reduce intra-user variability in the enrolled identifiers becomes novelly promising. This paper proposes a conventional iris authentication system and a hardware-friendly QC-LDPC error correction code scheme on a microprocessor-FPGA platform. Different QC-LDPC codes in IEEE 802.16e were analyzed and selected. Suitable codes were applied, followed by the evaluation experiments. The proposed design achieves a competitive result with up to 0.20% EER and 0.50% ZeroFAR on the CASIA-IrisV4-Syn database. Cryptographic keys with lengths of up to 288 bits can also be generated and recovered. Such a device can be potentially used for applications such as an access control system in high-security areas, identity verification at the borders, biometric cryptography and related authentication scenarios.

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“…Low-density parity-check (LDPC) codes [11], [12] are one of error correction codes which can be used to handle the errors in an error-prone communication channel. There have been comprehensive studies [13]- [15] on improving the complexity and accuracy of the LDPC decoders in communication fields such as applying appropriate calculations [16]- [19] and different structure of LDPC codes [20]- [22].…”

mentioning

confidence: 99%

An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes

Sham

et al. 2021

Preprint

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Extracting and analyzing iris textures for biometric recognition has been extensively studied. As the transition of iris recognition from lab technology to nationscale applications, most systems are facing high complexity in either time or space, leading to unfitness for embedded devices. In this paper, the proposed design includes a minimal set of computer vision modules and multi-mode QC-LDPC decoder which can alleviate variability and noise caused by iris acquisition and follow-up process. Several classes of QC-LDPC code from IEEE 802.16 are tested for the validity of accuracy improvement. Some of the codes mentioned above are used for further QC-LDPC decoder quantization, validation and comparison to each other. We show that we can apply Dynamic Partial Reconfiguration technology to implement the multi-mode QC-LDPC decoder for the iris recognition system. The results show that the implementation is power-efficient and good for edge applications.

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A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications

Cited by 9 publications

References 21 publications

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

An Effective Multi-Mode Iris Authentication System on a Microprocessor-FPGA Heterogeneous Platform With QC-LDPC Codes

An Embedded Iris Recognition System Optimization using Dynamically ReconfigurableDecoder with LDPC Codes

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