2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers 2006
DOI: 10.1109/isscc.2006.1696297
|View full text |Cite
|
Sign up to set email alerts
|

A 22GS/s 5b adc in 0.13/spl mu/m SiGe BiCMOS

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1

Citation Types

0
8
0

Year Published

2008
2008
2021
2021

Publication Types

Select...
4
3
2

Relationship

0
9

Authors

Journals

citations
Cited by 20 publications
(8 citation statements)
references
References 5 publications
0
8
0
Order By: Relevance
“…In realizing waveform storage with such delays, analog implementations can be quite demanding [24], while digital ones have to deal with the practical limitations of current ADC technology, [25], [26]. Thus, it is meaningful to quantify the BER sensitivity of the proposed MSDD detectors to the quantization errors, when the ADC resolution is limited to a few bits per sample at a sampling rate around the Nyquist rate.…”
Section: E Ber Sensitivity To Adc Resolutionmentioning
confidence: 99%
See 1 more Smart Citation
“…In realizing waveform storage with such delays, analog implementations can be quite demanding [24], while digital ones have to deal with the practical limitations of current ADC technology, [25], [26]. Thus, it is meaningful to quantify the BER sensitivity of the proposed MSDD detectors to the quantization errors, when the ADC resolution is limited to a few bits per sample at a sampling rate around the Nyquist rate.…”
Section: E Ber Sensitivity To Adc Resolutionmentioning
confidence: 99%
“…Bearing in mind that the optimum path to each of the 2 L−1 states in each stage depends on the values of two different branch metrics (this means 2L additions either in floating-point for the VA-SMSDD or in integer format for the VA-HMSDD), as can be deduced from (26), the total number of additions required for a block size of length M is approximately S VA = LM · 2 L , i.e., exponentially in the memory length L, but only linearly in the data block size M . Like the VA-MSDD, the SD-MSDD also builds on additions only, but its computational complexity is a random variable depending on not only M but also the received signal [28], in that the latter affects the choice of the sphere radius performed at each iteration (refer to Section IV for details).…”
Section: F Computational Complexitymentioning
confidence: 99%
“…These issues can be overcome by digitization with little or no TI at all, but then the whole ADC is required to operate at full speed. SiGe bipolar technologies have a reputation for having a very high speed potential, and several IC designers have taken advantage of it to built ADCs without time interleaving beyond 10 GS/s Nyquist-rate [3]- [6]. However, the high speed operation has required multiple watts of power dissipation in the past.…”
Section: Introductionmentioning
confidence: 99%
“…On the other hand, digital UWB receivers provide flexibility and benefit from CMOS technology scaling, but require an ADC sampling at Nyquist rate which is hardly realizable and highly power consuming, such as [7]. As the ADC power consumption of Flash ADCs, the standard solution for digital UWB architectures, scales linearly with the sampling rate and as a factor close to 4 with the bit width [8], several high speed 1-bit digital receiver architectures have been proposed, e.g.…”
Section: Introductionmentioning
confidence: 99%