A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation

Abstract

This paper describes a 23-GHz digital bang-bang phase-locked loop (PLL) fabricated in 65-nm CMOS for millimeter-wave frequency-modulated continuous-wave radars. The presented circuit aims to generate a fast sawtooth chirp signal that grants significant advantages with respect to the more conventional triangular waveform. Such a signal, however, features a very large bandwidth that requires the adoption of a two-point injection scheme. This paper, after intuitively discussing how the nonlinearity of the digitally controlled oscillator affects the accuracy of frequency modulation, presents a novel automatic pre-distortion engine, operating fully in background, which linearizes the tuning characteristic. The 19.7-mA fractional-N PLL having an rms jitter of 213 fs and an in-band fractional spur of −58 dBc is capable of synthesizing fast chirps with 173-MHz/µs maximum slope and an idle time of less than 200 ns after an abrupt frequency step with no over or undershoot.

A 23-GHz Low-Phase-Noise Digital Bang–Bang PLL for Fast Triangular and Sawtooth Chirp Modulation

“…In the fractional-N mode, the far-out phase noise exhibits a slight increment, increasing the absolute jitter from 213 fs (in the integer-N mode) to about 242 fs (in the fractional-N mode). In-band fractional spur is below −58 dBc [16].…”

“…In this paper, we introduce a 23-GHz DPLL for fast chirp generation, in which a wide bandwidth is obtained by adopting the two-point injection technique, while, at the same time, the nonlinear tuning curve of the digitally controlled oscillator (DCO) is calibrated in background by means of a novel digital predistortion (DPD) algorithm running fully in the background [16]. This paper is organized as follows.…”

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

“…In [8], the spur levels appear to have been incorrectly taken from PN plots without accounting for the resolution BW. In [10], with the sophisticated DTC nonlinearity calibration, a lower fractional spur of −38 dBc (normalized to 60 GHz) was achieved. There is no DTC/TDC nonlinearity calibration done in our design, but it can be applied if the spurs need further suppression in some applications.…”

“…Similar approaches (i.e., 125-MHz FREF, wide BW, and fine-resolution TDC) are adopted in the W -band ADPLL in [9]. In [10], low IPN was achieved in a fractional-N ADPLL with a fine-resolution (310 fs) digital-to-time converter (DTC) and 20-GHz digitally controlled oscillator (DCO). However, complicated digital predistortion algorithms were necessary to improve the DTC linearity.…”

A Hybrid Digital Transmitter Architecture for High- Efficiency and High-Speed Applications

“…Polar transmitter (Polar-TX) with 50% duty cycle clock features high efficiency but requires a high-speed and highresolution (10 bits or more) phase modulator that can be implemented by phase locking loop (PLL) [1] or phase shifter [2]. To achieve low clock jitter, the PLL requires a narrow loop bandwidth, which makes difficult high-speed phase modulation.…”