A 24-GHz Fully Integrated CMOS Transceiver for FMCW Radar Applications

Su, Yi-Pei; Huang, Chao-Yen; Chen, Sao-Jie

doi:10.1109/jssc.2021.3095137

Cited by 9 publications

(4 citation statements)

References 28 publications

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“…Radar applications for driver assistance systems and autonomous vehicles have pushed the development of frequency-modulated continuous-wave (FMCW) radars. FWCM radar provides advantages including high velocity and range resolution, exceptional environmental adaptability, and straightforward configuration [1,2]. Both 24 GHz and 77 GHz frequencies are commonly used in FMCW applications.…”

Section: Introductionmentioning

confidence: 99%

A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth

Zhang,

Lu,

et al. 2024

IEICE Electron. Express

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This article presents a high-linear phase-locked-loop-based (PLL-based) frequency-modulated continuous-wave (FMCW) frequency synthesizer for 77 GHz automotive radar applications. A behavioral model of the rms FM error by constructing the PLL transient response under a unit frequency step and taking into account the slope of the chirp signal is developed. Simulation results demonstrate the effectiveness of the proposed model in optimizing chirp linearity. The behavioral model is used to facilitate the design of the 77 GHz FMCW synthesizer fabricated in a 55 nm CMOS process. A gain linearized varactor approach is also developed to linearize the voltage-controlled oscillator (VCO) gain (𝐾 𝑉𝐶𝑂 ) to ensure constant PLL bandwidth maintaining optimum chirp linearity. Measurement results show that the synthesizer achieves a 1.2 GHz chirp bandwidth, a minimum rms FM error of 42 kHz (0.0035% of the chirp bandwidth) under a 4.219 MHz/𝜇s chirp slope while consuming 74.6 mW of power. The measured integer-N mode and fractional-N mode phase noises normalized to 78 GHz are -81.6 dBc/Hz and -80.1 dBc/Hz at 1 MHz offset, respectively.

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Section: Introductionmentioning

confidence: 99%

A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth

Zhang,

Lu,

et al. 2024

IEICE Electron. Express

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“…For example, an FMCW radar system being implemented by combining discrete radio frequency integrated chips (RFICs) on a printed circuit board (PCB) has large size, high cost, and high system complexity. In order to solve these problems, several works have been established to integrate discrete integrated chips (ICs), such as a transmitter (TX), a receiver (RX), and local oscillator (LO), into a single chip [ 5 , 6 , 7 , 8 , 9 ]. However, although the previous works have unique advantages in terms of the number of TX-RX channels and power consumption, there are still considerable shortcomings regarding the size and cost-effectiveness of FMCW radar applications.…”

Section: Introductionmentioning

confidence: 99%

“…Another requirement for the FMCW radar is a fast chirp generation capability. In [ 9 ], a fully integrated 1TX and 2-RX radar transceiver was presented using complementary metal oxide semiconductor (CMOS) technology. However, the slow-chirp waveform with ramp duration > 1 ms was used in a target detection scenario.…”

Section: Introductionmentioning

confidence: 99%

Fully Integrated 24-GHz 1TX-2RX Transceiver for Compact FMCW Radar Applications

Ko,

Moon,

Kim

et al. 2024

Sensors

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A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is −80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm2 die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets.

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“…Over the past few years, there has been significant advancement in the development of CMOS automotive radar receivers [1,2]. Moving to a higher operating frequency allows for a broader available bandwidth, leading to improved range, velocity, and angular resolution [3,4]. Similarly, sixth-generation (6G) wireless communication is predicted to surpass fifth-generation (5G) with boosted data rates and speeds of wireless systems.…”

mentioning

confidence: 99%

A mm‐wave LNA employing current re‐use and non‐linearity cancellation in 28 nm CMOS for automotive RADAR and 6G receivers

Kalita,

Khan,

Rahman

2024

Electronics Letters

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This letter reports an 85 GHz low noise amplifier (LNA) employing derivative superposition based non‐linearity cancellation and a current re‐use topology. The LNA employs a two‐stage stacked architecture, each featuring neutralized differential pairs utilizing the same DC current. In derivative superposition, an auxiliary branch consisting of neutralized differential pairs cells is added in the LNA in parallel to stage 1 to ensure non‐linearity cancellation. Layout‐based capacitive neutralization is implemented to improve GMAX, resulting in simplified routing, reduced parasitics, and a more compact layout. The proposed LNA is fabricated in TSMC 28 nm CMOS process and achieves a peak gain of 8.4 dB at 84.2 GHz with a measured 3 dB bandwidth () from 79.4 to 92 GHz. The minimum measured noise figure is 12.8 dB. The LNA draws 34 mA of DC current from a 1.2 V supply. The highly linear LNA with IIP3 +6.5 dBm is tailored for automotive RADAR and 6G receivers.

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A 24-GHz Fully Integrated CMOS Transceiver for FMCW Radar Applications

Cited by 9 publications

References 28 publications

A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth

A high-linear PLL-based FMCW frequency synthesizer with 42-kHz rms FM error and 1.2-GHz chirp bandwidth

Fully Integrated 24-GHz 1TX-2RX Transceiver for Compact FMCW Radar Applications

A mm‐wave LNA employing current re‐use and non‐linearity cancellation in 28 nm CMOS for automotive RADAR and 6G receivers

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