A 242mW 10mm<sup>2</sup> 1080p H.264/AVC High-Profile Encoder Chip

Lin, Yu-Kun; Li, Dewei; Lin, Chia Feng; Kuo, Tzu-Yun; Wu, Sian-Jin; Tai, Wei-Cheng; Chang, Wei‐Cheng; Chang, Tian-Sheuan

doi:10.1109/isscc.2008.4523183

Cited by 33 publications

(36 citation statements)

References 5 publications

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“…In hardware implementation, various simplifications are often considered and implemented [2,3]. For example, search algorithm are designed to allow search ranges and cost calculations to be shared across different block sizes to reduce hardware complexity [4,5].…”

Section: Hevc Motion Estimation Architecturementioning

confidence: 99%

Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine

Sinangil

Chandrakasan

Sze

et al. 2012

2012 19th IEEE International Conference on Image Processing

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This paper presents a comparison between various High Efficiency Video Coding (HEVC) motion estimation configurations in terms of coding efficiency and memory cost in hardware. An HEVC motion estimation hardware model that is suitable to implement HEVC reference software (HM) search algorithm is created and memory area and data bandwidth requirements are calculated based on this model. 11 different motion estimation configurations are considered. Supporting smaller block sizes is shown to impose significant memory cost in hardware although the coding gain achieved through supporting them is relatively smaller. Hence, depending on target encoder specifications, the decision can be made not to support certain block sizes. Specifically, supporting only 64x64, 32x32 and 16x16 block sizes provide 3.2X on-chip memory area, 26X on-chip bandwidth and 12.5X off-chip bandwidth savings at the expense of 12% bit-rate increase when compared to the anchor configuration supporting all block sizes.

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Section: Hevc Motion Estimation Architecturementioning

confidence: 99%

Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine

Sinangil

Chandrakasan

Sze

et al. 2012

2012 19th IEEE International Conference on Image Processing

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“…In literature, there are some architectures of the H.264/AVC encoder intra prediction [2][3][4][5][6][7][8][9][10][11][12][13][14]. However, none of them supports all intra prediction modes available in High Profile.…”

Section: Introductionmentioning

confidence: 99%

Intra Prediction for the Hardware H.264/AVC High Profile Encoder

Roszkowski

Pastuszak

2013

J Sign Process Syst

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The hardware implementation of the intra prediction described in this paper allows the H.264/AVC encoder to achieve optimal compression efficiency in real-time conditions. The architecture has some features that distinguish it from other solutions described in literature. Firstly, the architecture supports all intra prediction modes defined in High Profile of the H.264/AVC standard for all chroma formats. Secondly, the architecture can generate predictions for several quantization parameters. Thirdly, the hardware cost is reduced as the same resources are used to compute prediction samples for all the modes. Fourthly, the high sample-generation rate enables the encoder to achieve high throughputs. Fifthly, 4×4 block reordering and interleaving with other modes minimize the impact of the long-delay reconstruction loop on the encoder throughput. The architecture is verified against the JM.12 reference model and within the real-time FPGA hardware encoder. The synthesis results show that the design can operate at 100 MHz and 200 MHz for FPGA Aria II and 0.13 μm TSMC technology, respectively. These frequencies allow the encoder to support 720p and 1080p video at 30 fps.

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“…Initially, most of the work done on H.264 was oriented toward its software implementation. However, in recent years the contributions to the hardware implementation of H.264 have increased greatly, enabling the implementation of fast architectures for real-time video applications (Lin et al, 2008) (Finchelstein et al, 2009) ). The initial version of H.264/AVC used a transform hierarchy based on three transforms that are computed in integer arithmetic, two of size 4×4 and one of 2x2.…”

Section: Introductionmentioning

confidence: 99%