Memory cost vs. coding efficiency trade-offs for HEVC motion estimation engine

Abstract

This paper presents a comparison between various High Efficiency Video Coding (HEVC) motion estimation configurations in terms of coding efficiency and memory cost in hardware. An HEVC motion estimation hardware model that is suitable to implement HEVC reference software (HM) search algorithm is created and memory area and data bandwidth requirements are calculated based on this model. 11 different motion estimation configurations are considered. Supporting smaller block sizes is shown to impose significant memory cost in hardware although the coding gain achieved through supporting them is relatively smaller. Hence, depending on target encoder specifications, the decision can be made not to support certain block sizes. Specifically, supporting only 64x64, 32x32 and 16x16 block sizes provide 3.2X on-chip memory area, 26X on-chip bandwidth and 12.5X off-chip bandwidth savings at the expense of 12% bit-rate increase when compared to the anchor configuration supporting all block sizes.

Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard

“…The search range size can be reduced at the expense of coding efficiency loss. The work in [18] quantifies this effect and reports up to 3.5% loss in coding efficiency when search range is reduced from ±64 to ±16. For frame resolutions up to 4K×2K, a larger search range is advantageous and this work uses ±64 in both directions for this analysis.…”

A highly parallel SAD architecture for motion estimation in HEVC encoder

“…In addition, the largest CTB size that can be processed in [10] is 32x32 instead of 64x64. Although, this architecture reduces the complexity of the ME unit, it increases the required bit rate by 3% [11]. In [12], Nalluri et al proposed a different SAD architecture for VBSME with parallel stages.…”

“…On the other hand, current CTB and its search window are stored in on-chip internal memory. A CTB with size of 64x64 needs 39KB to support its ± 64 search range [11]. Therefore, about 44KB on-chip memory and about 14MB off-chip memory are requisites to store reference and current frames with 2K resolution.…”

“…However, it cannot provide 30 2K resolutions fps real time video coding or higher. In addition, all proposed architectures [10][11][12] exploit parallelism at different levels with different strategies.…”

“…Profiling shows that ME unit reaches up to 96% of the encoding time [9], and SAD unit takes the majority of this complexity, especially in the case of CTB size 64x64, which can be divided into more than 600 PBs with different sizes. Sseveral hardware architectures were proposed to speed up the SAD unit for ME in HEVC [10][11][12].…”