A 25-Gbps 8-ps/mm transmission line based interconnect for on-chip communications in multi-core chips

Abstract

This paper presents a novel on-chip interconnect system for multi-core chips using transmission lines as shared media. It supports both point-to-point and broadcasting communications. Compared to network-on-chip approaches, it offers significant advantages in circuit complexity, energy efficiency and link latency. To demonstrate the scheme, a chip prototype with two 20-mm long transmission lines running in parallel and multiple transmitters/receivers (including 2:1 serializer/1:2 deserializer) was implemented in a 130-nm SiGe BiCMOS technology. The prototype can achieve a date rate of 25.4 Gb/s with an energy efficiency of 1.67 pJ/b in the measurement.

RETRACTED: An improved hybrid network‐on‐chip with flexible topology and frugal routing

“…The state‐of‐the‐art surfaces of these components were used as an upper bound. The surface area occupied by RF NoC is mainly due to the FFT/IFFT [36], the transmitters and receivers [32] and the transmission line [37]. The work of [36] also shows the evolution of the area of two FFTs of 1,024 and 4,096 points as a function of the sampling rate sought.…”

Hybrid bidirectional transceiver for multipoint‐to‐multipoint signalling across on‐chip global interconnects

“…Devices at lower technology node having lower supply voltage have better speed and higher energy efficiency for a given architecture. The proposed design has better energy efficiency than the architectures in [25, 26], even though implemented in lower technology node.…”