A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback

Lu, Cho-Ying; Onabajo, Marvin; Gadde, Venkata; Lo, Yung-Chung; Chen, Hsien-Pu; Periasamy, Vijayaramalingam; Silva-Martí­nez, J.

doi:10.1109/jssc.2010.2050942

Cited by 47 publications

(9 citation statements)

References 22 publications

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“…Using subranging or two-step architectures can facilitate the reduction of power consumption in ADCs [1,28]. The ADCs reported in [10,80] have similar two-step and subranging architectures.…”

Section: Power-efficient High-speed Medium-resolution Adcsmentioning

confidence: 99%

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

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This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6-8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

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Section: Power-efficient High-speed Medium-resolution Adcsmentioning

confidence: 99%

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

Self Cite

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“…In [5], an operational transconductance amplifier that uses feedforward compensation is proposed (Fig. 2).…”

Section: Circuit Level Implementationmentioning

confidence: 99%

“…4 which can be explained as follows: The first gain stage is a differential pair resistively loaded (transistors M 1N and M LP ) in order to compare with the circuit in [5]. The second stage is composed by the transistors M 2P and a NMOS differential pair (M 2N ) that used current mirrors as charge.…”

Section: Circuit Level Implementationmentioning

confidence: 99%

“…Henceforth, the circuit presented in 4 will be call PFFA. In [5] it mentioned that the amplifier maintains low gain variations despite PVT variations; therefore, a comparison between proposed amplifier and the proposed in [5] are made by using PVT simulations in order to prove the gain enhancement while maintaining the same or even less gain variations.…”

Section: Circuit Level Implementationmentioning

confidence: 99%

“…Power supply was set to 1.8 V and the used load capacitance was 1 pF. The amplifiers were designed to deliver the same output current maintaining a similar The main idea is to show that the PFFA amplifier has a similar performance compared to circuit proposed in [5] while improving the DC gain. Also, PVT simulations are made for both the PFFA and the FFA topologies.…”

Section: Simulations and Comparisonmentioning

confidence: 99%

See 2 more Smart Citations

Robust to PVT enhanced DC gain amplifier using no Miller capacitor feedforward compensation

Ortiz

2014

Analog Integr Circ Sig Process

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This paper presents an operational transconductance amplifier compensated in frequency with a feedforward path implemented with current mirrors. This concept eliminates the need of Miller capacitor and improves performance compared to traditional feedforward topologies in regard to DC gain. Gain enhancement is achieved because of the use of current mirrors which reduces the number of the conductances that are connected to the output and increasing output impedance. Moreover, common mode range is improved by the PMOS differential pair used in the feedforward stage. Simulations results for the designed circuit on the typical UMC 180 nm CMOS process, show a DC gain above 60 dB with a unity gain frequency of 511 MHz, a phase margin (PM) of 49 , a slew rate (SR) of 205 V/ls and a power consumption of 5.1 mW maintaining low variations in regard to process, voltage and temperature variations.

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Frontiers of ΣΔ Modulators: Trends and Challenges

Rosa

2013

CMOS Sigma‐Delta Converters

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A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback

Cited by 47 publications

References 22 publications

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Robust to PVT enhanced DC gain amplifier using no Miller capacitor feedforward compensation

Frontiers of ΣΔ Modulators: Trends and Challenges

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