A 250-GHz 12.6-dB Gain and 3.8-dBm P
 sat Power Amplifier in 65-nm CMOS Adopting Dual-Shunt Elements Based G
 max-Core

Yun, Byeonghun; Park, Dae‐Woong; Choi, Won-Jong; Mahmood, Hafiz Usman; Lee, Sang‐Gug

doi:10.1109/lmwc.2020.3046745

Cited by 14 publications

(7 citation statements)

References 8 publications

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“…Generally, the G max based gain boosting can be achieved by utilizing the LC resonance concept. Therefore, with an increase in transistor size, the required values of shunt inductance (X 3 ) become small [29]. In Fig.…”

Section: B Proposed Gmax Based Simultaneous Output Power-and Gain-matching Techniquementioning

confidence: 96%

A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core

et al. 2021

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This paper proposes a simultaneous output power-and gain-matching technique in a sub-THz power amplifier (PA) design based on a maximum achievable gain (G max ) core. The optimum combination of three-passive-elements-based embedding networks for implementing the G max -core is chosen considering the small-and large-signal performances at the same time. By adopting the proposed technique, the simultaneous output power-and gain-matching can be achieved, maximizing the small-signal power gain and large-signal output power simultaneously. A 150 GHz single-ended two-stage PA without power combining circuit is implemented in a 65-nm CMOS process based on the proposed technique. The amplifier achieves a peak power gain of 17.5 dB, peak power added efficiency (PAE) of 13.3 and 16.1 %, saturated output power (P sat ) of 10.3 and 9.4 dBm, and DC power consumption of 86.3 and 52.4 mW, respectively, under the bias voltage of 1.2 and 1 V, which corresponds to the highest PAE, gain per stage and P out per single transistor among other reported CMOS D-band PAs. INDEX TERMS Amplifier, power amplifier, CMOS, gain-boosting, maximum achievable gain (G max ), terahertz (THz), simultaneous conjugate matching, load-pull, 6G communication system.

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Section: B Proposed Gmax Based Simultaneous Output Power-and Gain-matching Techniquementioning

confidence: 96%

A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core

et al. 2021

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“…2 shows the proposed active core employing the gain boosting technique for the frequency doubler. The power gain of the active core reaches the maximum achievable gain (Gmax) by embedding the passive components [17]− [20]. The proposed active core, denoted as Gmax-core, is applied to the frequency doubler to obtain the required voltage waveforms from the maximum second harmonic power conditions.…”

Section: B Gmax-core Adopting Gain Boosting Techniquementioning

confidence: 99%

“…This paper focuses on the harmonic transition between the saturation and triode regions while preventing the active core (transistor) from entering the cutoff region. Various Gmaxcore-based amplifiers reported earlier [17], [18] operate in class-A. The class-A operation provides 360 degrees of conduction angle, and thus, the transistor does not enter the cutoff region.…”

Section: B Gmax-core Adopting Gain Boosting Techniquementioning

confidence: 99%

“…The class-A operation provides 360 degrees of conduction angle, and thus, the transistor does not enter the cutoff region. Furthermore, the same dc bias condition at input and output as in [17], [18] does not require an ac coupling capacitor nor the gate biasing circuit, which is a significant source of insertion loss at the sub-THz band. Hence, we propose the adoption of the Gmax-core for the maximum second harmonic power.…”

Section: B Gmax-core Adopting Gain Boosting Techniquementioning

confidence: 99%

“…The transistor parameters, such as Cgs, Cgd, Cds, Rg, Rds, and gm of the transistor, are simulated to be 82 fF, 29 fF, 44 fF, 0.94 Ohm, 43 Ohm, and 118 mS, respectively. By embedding the linear-lossless-reciprocal components, the maximum available gain (Gma) of the transistor can reach the Gmax [17]. As shown in Fig.…”

Section: A Operation Principle At Fundamental Frequencymentioning

confidence: 99%

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Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

et al. 2023

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This article presents a power-efficient frequency doubler employing gain boosting and harmonic-enhancing techniques. With a single transistor only, the gain boosting technique can reach the maximum achievable gain (Gmax) by adding embedded passive components, thereby obtaining high voltage swings. Then, the transistor's nonlinearity is essential, which is maximized by the harmonic transition scheme of the transistor operation along with high voltage swings. In addition, a harmonic reflector and a harmonic leakage canceller are employed for the second harmonic enhancement. The harmonic reflector prevents unwanted harmonic mixing by minimizing the incoming second harmonic current fed back to the input. The harmonic leakage canceller suppresses the leakage loss of the second harmonic current present at the output. Furthermore, thanks to a proposed dual-band output matching network, the output impedance is conjugately matched to achieve the Gmax at the fundamental frequency while it is matched to extract the second harmonic output power simultaneously. To verify the proposed techniques, the prototype was designed as a single-stage circuit that does not require additional amplifying stages, which led to higher power efficiency and lower chip area. Implemented in a 65-nm CMOS process, the measurement results show a saturated output power of 0.9 dBm and 3-dB bandwidth of 26 GHz (237−263 GHz), respectively, while requiring a chip area of 0.071 mm 2 . Total power efficiency, including the effect of injected signal power, is 2.87 % while consuming only 37 mW dc power.

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A novel gain‐boosting structure with Z‐embedding and parallel pre‐embedding network for amplifiers at near‐f_max frequencies

Xie

Wang

2023

Circuit Theory & Apps

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SummaryIn this paper, a novel gain‐boosting structure with Z‐embedding and parallel pre‐embedding network (Z/pre‐Y‐embedding) is proposed to improve the power gain of amplifier at near‐fmax frequencies. Gain‐plane approach has been adopted to study the proposed Z/pre‐Y‐embedding technique. Analytical formula has been derived to calculate the required embedding elements to achieve the upper limit of the maximum available gain. The proposed technique exhibits an attractive advantage that it can absorb the external parasitics of the transistor into the Z/pre‐Y‐embedding network. Based on the proposed gain‐boosting structure, a three‐stage amplifier is designed in a 130 nm SiGe process to verify the power gain improvement. It exhibits a power gain of 21.1 dB at 230 GHz, which is 11.1 dB higher than the three‐stage amplifier without any gain‐boosting technique.

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A 250-GHz 12.6-dB Gain and 3.8-dBm P _sat Power Amplifier in 65-nm CMOS Adopting Dual-Shunt Elements Based G _max-Core

Cited by 14 publications

References 8 publications

A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core

A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

A novel gain‐boosting structure with Z‐embedding and parallel pre‐embedding network for amplifiers at near‐f_max frequencies

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A 250-GHz 12.6-dB Gain and 3.8-dBm P sat Power Amplifier in 65-nm CMOS Adopting Dual-Shunt Elements Based G max-Core

Cited by 14 publications

References 8 publications

A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core

A D-Band Power Amplifier in 65-nm CMOS by Adopting Simultaneous Output Power-and Gain-Matched Gmax-Core

Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques

A novel gain‐boosting structure with Z‐embedding and parallel pre‐embedding network for amplifiers at near‐fmax frequencies

Contact Info

Product

Resources

About

A 250-GHz 12.6-dB Gain and 3.8-dBm P _sat Power Amplifier in 65-nm CMOS Adopting Dual-Shunt Elements Based G _max-Core

A novel gain‐boosting structure with Z‐embedding and parallel pre‐embedding network for amplifiers at near‐f_max frequencies