Abstract-In this paper, a new technique to realize lumped dual-band impedance transformers for arbitrary frequency-dependent complex loads is proposed. For the complex impedance transforming, closedform design equations are presented for a series-shunt and a shuntseries type and a concept of combination is also presented. They use the proposed equation of input impedance. This equation can easily and exactly obtain the input impedance of any two-port network using the ABCD matrix. Then in order to realize dualband operation, four topologies comprising two types and a design method are presented. This technique is numerically demonstrated by various examples with excellent results and it has advantages of simplicity, intuitiveness and versatility because it is a general solution for complex impedance transforming. The proposed dualband impedance transforming technique can be utilized for practical matching problems such as microwave amplifiers and other devices.

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This article presents a power-efficient frequency doubler employing gain boosting and harmonic-enhancing techniques. With a single transistor only, the gain boosting technique can reach the maximum achievable gain (Gmax) by adding embedded passive components, thereby obtaining high voltage swings. Then, the transistor's nonlinearity is essential, which is maximized by the harmonic transition scheme of the transistor operation along with high voltage swings. In addition, a harmonic reflector and a harmonic leakage canceller are employed for the second harmonic enhancement. The harmonic reflector prevents unwanted harmonic mixing by minimizing the incoming second harmonic current fed back to the input. The harmonic leakage canceller suppresses the leakage loss of the second harmonic current present at the output. Furthermore, thanks to a proposed dual-band output matching network, the output impedance is conjugately matched to achieve the Gmax at the fundamental frequency while it is matched to extract the second harmonic output power simultaneously. To verify the proposed techniques, the prototype was designed as a single-stage circuit that does not require additional amplifying stages, which led to higher power efficiency and lower chip area. Implemented in a 65-nm CMOS process, the measurement results show a saturated output power of 0.9 dBm and 3-dB bandwidth of 26 GHz (237−263 GHz), respectively, while requiring a chip area of 0.071 mm 2 . Total power efficiency, including the effect of injected signal power, is 2.87 % while consuming only 37 mW dc power.

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