A 256-channel, high throughput and precision time-to-digital converter with a decomposition encoding scheme in a Kintex-7 FPGA

Abstract

A: Field Programmable Gate Arrays (FPGAs) made with 28 nm and more advanced process technology have great potentials for implementation of high precision time-to-digital convertors (TDC), because the delay cells in the tapped delay line (TDL) used for time interpolation are getting smaller and smaller. However, the bubble problems in the TDL status are becoming more complicated, which make it difficult to achieve TDCs on these chips with a high time precision. In this paper, we are proposing a novel decomposition encoding scheme, which not only can solve the bubble problem easily, but also has a high encoding efficiency. The potential of these chips to realize TDC can be fully released with the scheme. In a Xilinx Kintex-7 FPGA chip, we implemented a TDC system with 256 TDC channels, which doubles the number of TDC channels that our previous technique could achieve. Performances of all these TDC channels are evaluated. The average RMS time precision among them is 10.23 ps in the time-interval measurement range of (0-10 ns), and their measurement throughput reaches 277 M measures per second. K: Front-end electronics for detector readout; Instrumentation and methods for time-offlight (TOF) spectroscopy; Timing detectors; Gamma camera, SPECT, PET PET/CT, coronary CT angiography (CTA)

Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods

“…As stated earlier, the bubble-free sub-TDL structure (or the decomposition developed independently at the same time [17]) can be used [18]. The main idea is to ease mismatch problems in the TDL by elongating the tap intervals [18].…”

“…It was negligible in terms of the LSB in earlier TDCs. Later it became pronounced in high-resolution TDCs in more advanced CMOS technologies (due to more severe mismatches between carry-chains), leading to bubble problems (unexpected transitions of logic states) and resulting in encoding errors [17], [20]. Traditional de-bubble operations can reduce bubbles or recognize signal transitions; however, they are inefficient and introduce extra logic resources [20].…”

“…Therefore, since then, there is no efficient WU TDC reported in UltraScale FPGAs. Our Approach: In 2018, the decomposition [17] and our sub-TDL [18] methods were proposed to efficiently remove bubbles and zero-width bins without consuming extra logic resources. Sub-TDL structures can even remove bubbles entirely [18].…”

Bubble-Proof Algorithm for Wave Union TDCs

“…Clusters can be also used to solve simple bubble errors (e.g., single and double bubbles as in [4]). However, using most advanced FPGA devices for TDC implementation it is common to observe bubbles even on eight subsequent bits [18] and then this method becomes insufficient. The clustering method can be combined with decomposition [18] (simultaneously proposed by another research group and called a sub-TDL [19]) to correct bubble errors.…”

“…However, using most advanced FPGA devices for TDC implementation it is common to observe bubbles even on eight subsequent bits [18] and then this method becomes insufficient. The clustering method can be combined with decomposition [18] (simultaneously proposed by another research group and called a sub-TDL [19]) to correct bubble errors. It is worth mentioning that all of these works investigate identification of a determined number of transitions.…”