2020
DOI: 10.1016/j.nima.2019.162891
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A 256 Pixelated SPAD readout ASIC with in-Pixel TDC and embedded digital signal processing for uniformity and skew correction

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Cited by 22 publications
(34 citation statements)
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“…When performing single-photon counting with analog SiPMs, these fluctuations blur the spectrum at high photon counts. With a PDC, each triggered SPAD raises a flag processed by the digital logic [ 41 , 42 , 46 , 47 , 48 ]. Most variations in the SPAD’s response are thus masked by the digital conversion performed by the quenching circuit which therefore provides a greater SPAD-to-SPAD variation immunity.…”
Section: Analog Versus Digital Spad Arraymentioning
confidence: 99%
See 3 more Smart Citations
“…When performing single-photon counting with analog SiPMs, these fluctuations blur the spectrum at high photon counts. With a PDC, each triggered SPAD raises a flag processed by the digital logic [ 41 , 42 , 46 , 47 , 48 ]. Most variations in the SPAD’s response are thus masked by the digital conversion performed by the quenching circuit which therefore provides a greater SPAD-to-SPAD variation immunity.…”
Section: Analog Versus Digital Spad Arraymentioning
confidence: 99%
“…In this scheme, a high fill-factor front side illuminated SPAD array is implemented on the first tier (dedicated SPAD process). The underneath electronics (second tier) is implemented in a chosen CMOS process according to the levels of complexity and functionality needed by the application [ 46 , 48 , 69 , 70 , 71 , 72 ].…”
Section: 2d Versus 3d Integrated Pdcmentioning
confidence: 99%
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“…The 5.5 ps RMS timing jitter was measured at a 5.1 ps LSB over a 4 ns dynamic range. The jitter was measured using the methods described in [3,4]. The performance of the proposed Vernier TDC is summarised in Table 1 with previously reported high-resolution TDCs.…”
mentioning
confidence: 99%