A 26–28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS

Sun, Li; Pan, Quan; Wang, Keh-Chung; Yue, C. Patrick

doi:10.1109/tcsi.2014.2304669

Cited by 9 publications

(6 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…3(a) shows the circuit diagram and design details of the presented pseudo-differential triple-inductive inverterbased TIA. Both the shunt-shunt inductive feedback (L f ) and input series peaking techniques (L s ) are adopted to extend the circuit BW [11,12,14] . This pseudo-differential TIA is optimized based on the single-ended topology presented in Ref.…”

Section: Optical Front-endmentioning

confidence: 99%

“…The phase detector is a linear type as explained in Ref. [13]. The voltage-to-current (V2I) circuits are charge pumps providing output currents to the third-order loop filter, generating the control voltages for the LC-type voltagecontrolled oscillator (VCO).…”

Section: Clock and Data Recovery Circuitmentioning

confidence: 99%

“…It should be noted that the TIA stage has been previously published in its single-ended topology [11,12] . In this work, an optimized pseudo-differential TIA with a TIA buffer is presented to alleviate the imbalance between its differential outputs.…”

Section: Introductionmentioning

confidence: 99%

“…The full-rate CDR has been presented in Ref. [10,13]. Based on these previous designs, this work focuses on research of the optical front-end, including TIA buffer, DC offset circuit, and digitally tuning gm-TIA variable-gain amplifiers (VGAs).…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

Pan¹,

Luo²,

Li³

et al. 2022

J. Semicond.

Self Cite

View full text Add to dashboard Cite

This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ transimpedance gain, 20.4-GHz −3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10−12 BER at 26 Gb/s for a 215−1 PRBS input with a −7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.

show abstract

Section: Optical Front-endmentioning

confidence: 99%

Section: Clock and Data Recovery Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

Pan¹,

Luo²,

Li³

et al. 2022

J. Semicond.

Self Cite

View full text Add to dashboard Cite

show abstract

“…T ECHNOLOGY scaling has motivated the evolution of a clock and data recovery (CDR) circuit which is an essential block in high-speed serial links to recover the clock and the data from the jittery input data [1]- [5]. A conventional CDR, which is implemented with analog circuitry, such as a charge pump and an analog low-pass loop filter (LF), suffers from the following problems.…”

Section: Introductionmentioning

confidence: 99%

A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta–Sigma Modulator

Lee

Kim

Sim

et al. 2016

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

A digital clock and data recovery (CDR) employing a time-dithered delta-sigma modulator (TDDSM) is presented. By enabling hybrid dithering of a sampling period as well as an output bit of the TDDSM, the proposed CDR enhances the resolution of digitally controlled oscillator, removes a low-pass filter in the integral path, and reduces jitter generation. Fabricated in a 65-nm CMOS process, the proposed CDR operates at 5-Gb/s data rate with BER < 10 −12 for PRBS 31. The CDR consumes 13.32 mW at 5 Gb/s and achieves 2.14 and 29.7 ps of a long-term rms and peak-to-peak jitter, respectively.Index Terms-Delta-sigma modulator (DSM), digital clock and data recovery (CDR), digitally controlled oscillator (DCO), high-speed serial link, hybrid dithering, loop delay, resolution, time-dithered DSM (TDDSM).

show abstract

A 0.13-μm CMOS resonator-based frequency-doubling mechanism for clock recovery in a full-rate 40 Gb/s optical receiver

Chong

Pour

2021

Microelectronics Journal

View full text Add to dashboard Cite

A 26–28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS

Cited by 9 publications

References 11 publications

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

A 26-Gb/s CMOS optical receiver with a reference-less CDR in 65-nm CMOS

A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta–Sigma Modulator

A 0.13-μm CMOS resonator-based frequency-doubling mechanism for clock recovery in a full-rate 40 Gb/s optical receiver

Contact Info

Product

Resources

About