Micro‐LED is superior to LCD and OLED in terms of power consumption, light efficiency, contrast, response time, reliability, color gamut, lifetime, resolution and viewing angle, it is regarded as the most promising display technology in next generation. However, there are still many technical bottlenecks that hinder the development of Micro‐LED display. One of the most important technical issues is mass transfer. Mass transfer is a technology aim to transferring millions or even tens of millions of Micro‐LED pixels which grown on sapphire substrates to the glass substrates required for display devices quickly and correctly and providing good electrical and mechanical connections between the Micro‐LED pixels and the drive circuits. There have been many companies that have been working to solve this problem and have come up with solutions from different technical aspects. In this paper, we will review several different technologies, classify them from the technical type, evaluate the maturity and achievability of the technology, and analyze the application fields of different technologies.

This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process. Multiple bandwidth enhancement techniques, including input bonding wire, input series on-chip inductive peaking and negative capacitance compensation, are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device, achieving an overall bandwidth enhancement ratio of 8.5. The electrical measurement shows TIA achieves 58 dBΩ up to 12.7 GHz with a 180-fF off-chip photodetector. The optical measurement demonstrates a clear open eye of 20 Gb/s. The TIA dissipates 4 mW from a 1.2-V supply voltage.

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This paper presents a 26-Gb/s CMOS optical receiver that is fabricated in 65-nm technology. It consists of a triple-inductive transimpedance amplifier (TIA), direct current (DC) offset cancellation circuits, 3-stage gm-TIA variable-gain amplifiers (VGA), and a reference-less clock and data recovery (CDR) circuit with built-in equalization technique. The TIA/VGA front-end measurement results demonstrate 72-dBΩ transimpedance gain, 20.4-GHz −3-dB bandwidth, and 12-dB DC gain tuning range. The measurements of the VGA’s resistive networks also demonstrate its efficient capability of overcoming the voltage and temperature variations. The CDR adopts a full-rate topology with 12-dB imbedded equalization tuning range. Optical measurements of this chipset achieve a 10−12 BER at 26 Gb/s for a 215−1 PRBS input with a −7.3-dBm input sensitivity. The measurement results with a 10-dB @ 13 GHz attenuator also demonstrate the effectiveness of the gain tuning capability and the built-in equalization. The entire system consumes 140 mW from a 1/1.2-V supply.