A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

Tachibana, Fumihiko; Hirabayashi, O.; Takeyama, Y.; Shizuno, Miyako; Kawasumi, A.; Kushida, K.; Suzuki, Ai; Niki, Yusuke; Sasaki, Shinya; Yabe, T.; Unekawa, Yasuo

doi:10.1109/jssc.2013.2280312

Cited by 14 publications

(6 citation statements)

References 6 publications

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“…So, from (7)(8)(9), it is clear that the charge recycling technique reduces the energy dissipation and this reduces the current leakage during transition modes and reduction in leakage current finally causes the reduction of static power dissipation of the proposed SRAM cell.…”

Section: Energy Saving Ratio and Static Power Dissipationmentioning

confidence: 99%

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A design of low swing and multi threshold voltage based low power 12T SRAM cell

Upadhyay

Kar

Mandal

et al. 2015

Computers & Electrical Engineering

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Section: Energy Saving Ratio and Static Power Dissipationmentioning

confidence: 99%

“…In [8], a technique to reduce both the active and standby powers, especially at room temperature, has been discussed. A bit line power calculator is used to adaptively set the cell supply voltage in the active mode.…”

Section: Introductionmentioning

confidence: 99%

A design of low swing and multi threshold voltage based low power 12T SRAM cell

Upadhyay

Kar

Mandal

et al. 2015

Computers & Electrical Engineering

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“…An additional SRAM unit (PKT-RAM-US) is needed for storage of upstream packets. Assuming that PKT-RAM-DS is sized to store the complete payload of one XG-PON downstream frame, the total memory requirement for the XG-PON ONT is assumed to be about 2 Mbits and its total dynamic and static power is estimated to be between 1 and 2 mW [31], which is negligible compared to P daX . SRAM power in the Bi-PON ONT are even lower, because the maximum Bi-PON downstream user size is 8 times lower than that in XG-PON, which would allow for proportional scaling of the FEC-RAM and PKT-RAM-DS sizes.…”

Section: A Digital Power Consumption Modelsmentioning

confidence: 99%

A Low-Energy Rate-Adaptive Bit-Interleaved Passive Optical Network

Suvakovic¹,

Chow²,

Anthapadmanabhan³

et al. 2014

IEEE J. Select. Areas Commun.

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Abstract-Energy consumption of customer premises equipment (CPE) in the new generation of time-division multiplexing (TDM) passive optical networks (PON) operating at 10 Gb/s, has become a serious problem both in terms of the global network energy consumption and the CPE battery life. The proposed low energy passive optical network (PON), based on a novel bitinterleaving downstream protocol, reduces the protocol processing energy by a factor of 30 and enables a significant reduction in the total CPE energy consumption over the standard 10 Gb/s PON CPE. The network architecture, protocol and the key enabling techniques for its implementation, including dynamic traffic interleaving, rate-adaptive descrambling of decimated traffic and downsampling clock and data recovery (CDR) circuit, are described. Detailed analysis of the CPE energy consumption and comparison with the standard PON CPE is also included in the paper.

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“…From Fig. 3, the type 1 devices perform two detection levels and a Owing to the energy-saving topic, many researches put much emphasis on the power conversion efficiency [6][7][8][9][10][11][12][13] and standby power losses of converter [14,15]. However, some PDs have low power modes or standby modes and for this reason it may be removed by the PSE.…”

Section: Introductionmentioning

confidence: 99%

Adaptive maintain power signature scheme for power over ethernet system

Zhu

2020

IET Power Electronics

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Power over Ethernet (PoE) technology has been widely used in networking market for its space-saving, flexibility and low cost. As the PoE system needs to meet maintain power signature (MPS) requirements specified by the IEEE standard, it is important for powered device (PD) to draw a predetermined minimum current. If the PD current goes below the minimum current, the power sourcing equipment (PSE) assumes the PD has been disconnected and terminates operating voltage. If a fixed current is added to exceed the minimum current, a phenomenon of power wasting will be caused during standby or ultralow power mode. This study proposes an adaptive MPS scheme to achieve power-saving and meet the MPS requirements. It consists of current comparator and MPS circuit to extract the periodic pulsed current for MPS requirements. The proposed scheme has been fabricated in 0.18 μm 100 V Bipolar-CMOS-DMOS process adding no extra pin and an area is 1.45 × 2.23 mm 2. Test results show that the proposed interface sources a periodic pulsed current with a period of 318 ms and 25% duty cycle to tackle the issue of MPS absence in very low power condition.

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A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

Cited by 14 publications

References 6 publications

A design of low swing and multi threshold voltage based low power 12T SRAM cell

A design of low swing and multi threshold voltage based low power 12T SRAM cell

A Low-Energy Rate-Adaptive Bit-Interleaved Passive Optical Network

Adaptive maintain power signature scheme for power over ethernet system

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