A 283 GHz low power heterodyne receiver with on-chip local oscillator in 65 nm CMOS process

Guerra, José Moron; Siligaris, Alexandre; Lampin, Jean‐François; Danneville, F.; Vincent, Pierre

doi:10.1109/rfic.2013.6569588

Cited by 16 publications

(2 citation statements)

References 6 publications

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“…A major advantage of injection locking is an output phase noise of the oscillator equal to its input phase noise. ILO based frequency multi plication is currently limited to small factors (2)(3)(4)(5). In this work, an original use of an injected oscillator is presented.…”

Section: Introductionmentioning

confidence: 99%

A novel harmonic selection technique based on the injection of a periodically repeated oscillations train into an oscillator

Jany

Siligaris

Ferrari

et al. 2014

2014 IEEE MTT-S International Microwave Symposium (IMS2014)

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A new concept based on the injection of a period icall y repeated oscillations train into an oscillator is presented.It is based on a phenomenon named pseudo-locking, leading to a novel harmonic selection technique. Theoretical description of the concept is presented, in particular an anal y tical condition is carried out, paving the wa y of design rules. For a proof of concept, an oscillator fabricated on a 40 nm CMOS technolog y was measured. The concept was validated b y measured phase noise equivalent to classical fundamental injection locking phase noise performance.

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Section: Introductionmentioning

confidence: 99%

A novel harmonic selection technique based on the injection of a periodically repeated oscillations train into an oscillator

Jany

Siligaris

Ferrari

et al. 2014

2014 IEEE MTT-S International Microwave Symposium (IMS2014)

Self Cite

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“…These mixers provide good port-to-port isolation and conversion gain. Nevertheless, some recent works have reported 60 GHz single-ended [4], [5] and single-balanced [6] resistive mixers using 90, 130, and 65 nm CMOS process respectively, and more recently, a 65 nm CMOS single-balanced resistive mixer has been demonstrated at 283 GHz in a sub-harmonic configuration [7]. Despite conversion losses, these resistive mixer topologies exhibit better linearity and better noise performances, particularly for zero-IF receivers because the absence of flicker noise.…”

Section: Introductionmentioning

confidence: 99%

NMOS Device Optimization for the Design of a W-Band Double-Balanced Resistive Mixer

Viallon

Ménéghin

Parra

2014

IEEE Microw. Wireless Compon. Lett.

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This letter describes the implementation of NMOS devices in a passive ring mixer whose operating frequency reaches device's cut-off frequency. Conversion gain, linearity and required LO power are discussed regarding device geometry using simple analytic formulas and electrical simulations. The mixer is then embedded in a down-converter including RF, LO and IF buffers and integrated in a 130 nm BiCMOS SiGe technology. Measurements indicate a conversion gain of 14.5 dB at 76.8 GHz, an output-referred 1 dB compression point of and a DSB noise figure of 6.3 dB confirming the interest of double-balanced passive mixers at millimeter-wave frequencies.

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500 GHz CMOS heterodyne imager adopting fourth subharmonic passive mixer

Choi

Park

Utomo

et al. 2019

Micro & Optical Tech Letters

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A 500 GHz heterodyne imager adopting a source‐driven fourth subharmonic single balanced resistive mixer is implemented in 65‐nm CMOS technology. The adopted passive mixer improves the port‐to‐port isolation and minimizes the input matching loss. At an LO power of 5 dBm, the imager achieves a conversion loss and double sideband noise figure of 30.2 dB and 51 dB, respectively, which corresponds to −93 dBm and 15.8 fW/Hz0.5 of sensitivity and the effective noise equivalent power, respectively, assuming a noise bandwidth of 1 kHz. To the best of authors' knowledge, the proposed work is the highest frequency implementation as a CMOS‐based heterodyne imagers adopting resistive mixers.

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A 283 GHz low power heterodyne receiver with on-chip local oscillator in 65 nm CMOS process

Cited by 16 publications

References 6 publications

A novel harmonic selection technique based on the injection of a periodically repeated oscillations train into an oscillator

A novel harmonic selection technique based on the injection of a periodically repeated oscillations train into an oscillator

NMOS Device Optimization for the Design of a W-Band Double-Balanced Resistive Mixer

500 GHz CMOS heterodyne imager adopting fourth subharmonic passive mixer

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