A 2T-MONOS Embedded Flash Macro With 65-nm SOTB Technology Achieving 0.15-pJ/bit Read Energy With 80-MHz Access for IoT Applications

This work numerically elucidates the effects of transverse scaling on Schottky barrier charge-trapping cells for energy-efficient applications. Together with the scaled gate structures and charge-trapping dielectrics, variations in bias conditions on source-side injection are considered for properly operating Schottky barrier cells in low-power or high-efficiency applications. A gate voltage of 5 to 9 V with a drain voltage of 1 to 3 V was employed to program the Schottky barrier cells. Both the non-planar double-gate gate structure and scaled dielectric layers effectively improve the source-side programming. When the gate voltage of 5 V was operated, there were roughly two orders of magnitude greater injected gate currents observed in the ONO-scaled double-gate cells. Five successive programming-trapping iterations were employed to consider the coupling of trapped charges and Schottky barriers, examining the differences in physical mechanisms between different design options. The gate structures, dielectric layers, and gate/drain voltages are key factors in designing transverse scaled Schottky barrier charge-trapping cells for low-power and high-efficiency applications.

show abstract

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

customersupport@researchsolutions.com

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

A 2T-MONOS Embedded Flash Macro With 65-nm SOTB Technology Achieving 0.15-pJ/bit Read Energy With 80-MHz Access for IoT Applications

Cited by 3 publications

References 8 publications

Structural and electrical behaviors of silicon nitride thin-films deposited using spin coating technique

Structural and electrical behaviors of silicon nitride thin-films deposited using spin coating technique

Transverse dielectric and lateral channel band engineering of drain-side and source-side injection in Ge-based charge-trapping memory cells for energy-efficient applications

Transverse Scaling of Schottky Barrier Charge-Trapping Cells for Energy-Efficient Applications

Contact Info

Product

Resources

About