A 2x2 bit Vedic multiplier with different adders in 90nm CMOS technology

Jie, Lee Shing; Ruslan, Siti Hawa

doi:10.1063/1.5002035

Cited by 8 publications

(3 citation statements)

References 3 publications

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“…1 shows an example of the basic 4x4 bit multiplication by using multiple adders and logic gates [4,5,6,7,8,9,10,11]. The process of multiplication is based on addition, and many of the techniques useful in addition carry over to multiplication [4,5]. The multiplication of Y0 and X0 which will produce a partial product Y0X0 that can be gained by using an AND gate.…”

Section: Mathematical Formulationmentioning

confidence: 99%

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Design of Complex Multiplier Using Vedic Mathematics

Hassan,

Hwa,

Akhball

et al. 2023

IJIE

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In this project, a 4x4 multiplier is implemented that utilizes the Urdhava Tiryakbhyam sutra method in Vedic mathematics. This method is applicable in all two decimal number multiplications which offers high speed calculation and improved efficiency. Thus, the design of a 4x4 Vedic-based multiplier is solely aimed at performing faster multiplications and achieving quicker processing speeds than the traditional multipliers. The architecture of the Vedic multiplier consists of four 2x2 multipliers and three adders of different bit sizes that are assembled using the Wallace tree implementation. The coding for the multipliers and adders is written in Verilog Hardware Description Language (HDL) in the Quartus Prime 17 Software. Functional simulation is then carried out to ensure that the Vedic multiplier performs the accurate multiplication operations, while the Verilog Compiled Simulator is employed to compile and simulate the multiplier design. Following this, the Design Compiler (DC) and Integrated Circuit Compiler (ICC) command scripts are then composed to allow the logic and physical synthesis to be performed on the Vedic and traditional multipliers. From there, the performance level of both these multipliers are assessed through reference to several key parameters such as timing, area, power consumption, overflow percentage and congestion statistics. Based on the results obtained in the synthesis process, the Vedic multiplier possesses faster operational speed than the traditional multiplier (due to a shorter processing time), butultimately exhibits a greater power consumption and wider area coverage.

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Section: Mathematical Formulationmentioning

confidence: 99%

“…This Sutra was traditionally used in ancient India for the multiplication of two decimal numbers in relatively less time [3]. The speed of a processor determines its performance [4,5,6,7,8]. High speed processing is an essential requirement for all the systems.…”

Section: Introductionmentioning

confidence: 99%

Design of Complex Multiplier Using Vedic Mathematics

Hassan,

Hwa,

Akhball

et al. 2023

IJIE

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“…In many processors and computers, adders are used in the Arithmetic Logic Unit (ALU). To conserve energy, adders with efficient power and speed consumption play a vital role in designing of vedic multipliers [11]. Different adders which are discussed below can be replaced by the adder block in Fig 5 . Some of the approaches for designing of vedic multiplier using different adder topologies are given below:…”

Section: Approaches For Adders Used In Designing Vedic Multipliermentioning

confidence: 99%

Comparative Analysis of Vedic Multiplier using Various Adder Architectures

Yadav

Kumar

Shareef

et al. 2022

J. Phys.: Conf. Ser.

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The performance of a microprocessor depends on the efficient multiplier as it is one of the most principal component in various digital circuits. This paper reviews optimization techniques for high speed Vedic multiplier design which is based on Urdhva Tiryakbhyam Sutra of Ancient Indian Vedic Mathematics. This particular sutra is the most efficient one as it gives minimum delay for all types of complex multiplication. Adder being the most important component in a multiplier design, using the efficient adder will enhance the performance of Vedic multiplier. During the comparison, different adder topologies like Carry Look ahead Adder, Kogge Stone Adder, Carry Skip Adder are used to compare area, delay and power. The reviewed methods are implemented on 45nanometer(nm), 90nm and 180 nm CMOS technology. The results of all the prior approaches are reviewed and an efficient method out of them has been proposed.

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