A 3.0-ps rms Precision 277-MSamples/s Throughput Time-to-Digital Converter Using Multi-Edge Encoding Scheme in a Kintex-7 FPGA

Wang, Yonggang; Zhou, X. Y.; Song, Zhiquan; Kuang, Jie; Cao, Qiang

doi:10.1109/tns.2019.2938571

Cited by 48 publications

(40 citation statements)

References 20 publications

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“…Although 20-chain TDCs [53] could have better INL performances with offset corrections, they require 127 DSP blocks and are complicated to implement due to chain-by-chain and chip-by-chip corrections. 2-stage interpolation TDCs [55] (with much more complex structures) used at least 1-or 2-fold more FFs than our 1-stage DSWU TDC, whereas WU TDCs in [44] consumed 2-fold more LUTs and FFs than our DSWU TDC. Moreover, our TDCs are more cost-effective in configurable logic blocks than matrix TDCs [56] and TDCs with large scale parallel routing methods [59]; our TDCs are much more suitable for multi-channel applications.…”

Section: Discussion and Comparisonsmentioning

confidence: 80%

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Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods

Xie

Chen

2022

IEEE Trans. Ind. Electron.

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The wave union (WU) method is a well-known method in time-to-digital converters (TDCs) and can improve TDC performances without consuming extra logic resources. However, an earlier study concluded that the WU method is not suitable for UltraScale fieldprogrammable gate array (FPGA) devices, due to more severe bubble errors. This paper proves otherwise and presents new strategies to pursue high-resolution TDCs in Xilinx UltraScale 20 nm FPGAs. Combining our new subtapped delay line (sub-TDL) architecture (effective in removing bubbles and zero-width bins) and the WU method, we found that the wave union method is still powerful in UltraScale devices. We also compared the proposed TDC with the TDCs combining the dual sampling (DS) structure and the sub-TDL technique. A binning method is introduced to improve the linearity. Moreover, we derived a formula of the total measurement uncertainties for a single-stage TDL-TDC to obtain its root-mean-square (RMS) resolution. Compared with previously published FPGA-TDCs, we presented (for the first time) much more detailed precision analysis for single-TDL TDCs.Index Terms-Carry chains, field-programmable gate array (FPGA), time-of-flight (ToF), time-to-digital converter (TDC) Manuscript

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Section: Discussion and Comparisonsmentioning

confidence: 80%

“…With sub-TDLs, bubbles can be easily removed, and the WU method is 'still' efficient in UltraScale FPGAs. A TDC using an 8-edge WU signal was proposed [44]; however, the encoding process is much more complicated. The sub-TDL should be modified if more edges are used, but it is out of this study's scope.…”

Section: Wave Union Methods With Sub-tdl To Remove Bubblesmentioning

confidence: 99%

Efficient Time-to-Digital Converters in 20 nm FPGAs With Wave Union Methods

Xie

Chen

2022

IEEE Trans. Ind. Electron.

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“…This method was first proposed by Wu and Shi in 2008 [1], and since then it has been used for various applications including nuclear physics [2,3], time interval counters [4], light detection and ranging (LiDAR) systems [5]. It has also undergone significant improvement during this time, making it possible to obtain the highest performance of TDCs in the FPGA technology in terms of the measurement rate, time resolution and precision [6][7][8]. However, in order for this to be possible, several design challenges have to be overcome.…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, some implementations in very high process node FPGA devices (e.g., 20 nm CMOS) consider only two transitions [15,16]. However, the highest precision converters often use multiple transitions, e.g., 6 [4] or 8 [8]. A certain solution to this expectation is the pre-encoder presented in [12].…”

Section: Introductionmentioning

confidence: 99%

“…The encoder is divided into so-called clusters and each of them is capable to detect 1-0 transitions. The proposed solution is intended to detect only one transition in a complete code but this idea (clustering) is extendable to more transitions [8]. A similar approach, multiple six taps windows (clusters) on the thermometer code value, was proposed in [17].…”

Section: Introductionmentioning

confidence: 99%

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Bubble-Proof Algorithm for Wave Union TDCs

2021

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Nowadays state-of-the-art time-to-digital converters (TDCs) are commonly implemented in field-programmable gate array (FPGA) devices using different variations of the wave union method. To take full advantage of this method many design challenges need to be overcome, one of which is an efficient data encoding. In this work, we describe in detail an effective algorithm to decode raw output data from a newly designed multisampling wave union TDC. The algorithm is able to correct bubble errors and detect any number of transitions, which occur in the wave union TDC output code. This allows us to reach a mean resolution as high as 0.39 ps and a single shot precision of 2.33 ps in the Xilinx Kintex-7 FPGA chip. The presented algorithm can be used for any kind of wave union TDCs and is intended for partial hardware implementation.

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