A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

Chi, Hyung-Joon; Lee, Jae Seung; Jeon, Seong-Hwan; Bae, Seung-Jun; Sim, Jae‐Yoon; Park, Hong-June

doi:10.1109/isscc.2008.4523082

Cited by 8 publications

(4 citation statements)

References 6 publications

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“…Single-ended signaling is mostly used in the DRAM interface instead of differential signaling to reduce the chip pin count for low cost (Fig. 1) [1], [2]. The parallel link is susceptible to the simultaneous switching noise (SSN) that is the transient L(di/dt) noise on the output driver power lines.…”

Section: Introductionmentioning

confidence: 99%

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

Lee

Lim

et al. 2016

IEEE J. Solid-State Circuits

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A four-bit four-wire four-level (4B4W4L) singleended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of ∼10 dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential sensing without a reference voltage at RX, to maintain the pin efficiency of 100%, and also to reduce EMI by setting the sum of currents through the four wires to be zero. A capacitive pre-emphasis scheme modified for four-level signaling is also used at TX to compensate for inter-symbol interference. The transmitted four-level signals are recovered by six differential comparators with an offset compensation and a decoder at RX. The proposed transceiver chip fabricated in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2 inch FR4 channel at 8 Gb/s. Index Terms-Balanced coding, DRAM interface, electromagnetic interference (EMI), H-field measurement, parallel links, single-ended, transceiver, 4-bit 4-wire 4-level signaling.

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Section: Introductionmentioning

confidence: 99%

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

Lee

Lim

et al. 2016

IEEE J. Solid-State Circuits

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“…The detailed circuit of the integrating summer is shown in Fig. 17.2.2, where the integrated output, y(t) can be represented as,This integrator helps to reduce power and increase the robustness to highfrequency noise [1,[4][5].Figure 17.2.3 shows the training mode operation to find the IDFE tap position for reflection (Rp1, Rp2) and the IDFE coefficients for ISI (Ic1) and reflection (Rc1, Rc2). During the training mode, a single-bit pulse pattern of length 16 (1000…000) is repeated with signal swing from V DD to 0.75V DD (V ref ) and the inputs of the ISI branch and two reflection branches of the integrating summer ( Fig.…”

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confidence: 99%

“…This integrator helps to reduce power and increase the robustness to highfrequency noise [1,[4][5]. shows the training mode operation to find the IDFE tap position for reflection (Rp1, Rp2) and the IDFE coefficients for ISI (Ic1) and reflection (Rc1, Rc2).…”

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confidence: 99%

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z<inf>0</inf> at both TX and RX

Lee

Kim

et al. 2013

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

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The transceiver power is reduced by 27% in the single-ended point-to-point DRAM interface by increasing the termination resistance to 4×Z 0 at both ends of TX and RX. The resultant increase of ISI and reflection is compensated for at RX by using the 1-tap and 2-tap integrating decision-feedback equalizer (IDFE), respectively, where the reflection tap position and the tap coefficients are found automatically during the training mode. This improves the bathtub opening of a 4-inch FR4 channel from 20% to 62.5% at 5Gb/s in 0.13μm CMOS.As the data rate for the chip-to-chip interface of DRAM reaches several Gb/s, the I/O interface circuit consumes around 20 to 30% of the total chip power. Recently, there is a strong demand for low power in the mobile DRAM interface without reducing the data rate. In the DRAM interface with the single-ended signaling, the output driver dominates the power consumption. However, the output driver power is almost fixed because of the termination requirements at both TX and RX as well as the fixed signal swing. The pseudo open drain (POD) driver ( Fig. 17.2.1) is usually used as output driver in the DRAM interface [1,2]. The output voltage swing cannot be reduced significantly because of the environmental noise and input offset voltage at RX. In the POD driver, the output voltage swing is fixed at 0.5V DD (V DD -0.5V DD ), where the energy per bit spent by output driver is 0.5V DD 2 (0.25C T + 0.5T/R T ), where C T is the total capacitance of transmission channel including the chip pin capacitance and T is the data period. It assumes the equal probability for data '1' and '0'. If the termination resistance R T is fixed at Z 0 (characteristic impedance of transmission line), the energy per bit of output driver is fixed. In this work, R T is deliberately increased to 4×Z 0 to reduce the output driver power. This increases both ISI and reflection, which are compensated for at RX by using the IDFE circuit with 2 taps for reflection and 1 tap for ISI. For the write operation into DRAM chips, the IDFE circuit must be implemented in DRAM. This is an overhead in DRAM. However, with the scaled down technology, the area and power consumption of IDFE will be reduced further.The single-pulse response and eye-diagram for R T = Z 0 and R T = 4×Z 0 are shown in Fig. 17.2.1 at 5Gb/s for a 4-inch FR4 channel. For R T = 4×Z 0 , the amplitude of main pulse is reduced by 0.64 and the significant increase of reflection and ISI can be observed. To compensate for the ISI and reflection using the 3-tap IDFE circuit at RX, we need the IDFE tap positions (Rp1, Rp2) corresponding to the reflection point as well as the IDFE coefficients for ISI (Ic1) and reflection (Rc1, Rc2). While the ISI occurs during the data period next to the main pulse, the reflection point occurs after 2t f from the main pulse, where t f is the time of flight of the transmission channel. The IDFE tap position for reflection point from the main pulse is determined by the product of 2t f and the data rate. To find the values of Rp1, Rp2, Ic1, Rc...

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“…While a DFE [1] can be used to compensate channel distortion, its power dissipation reduces link energy efficiency, which is vitally important in complex systems. One way of reducing DFE power consumption is to use current-integrating summers [2][3][4][5]. Previously published current-integrating DFEs operating above 5Gb/s [3,5] were demonstrated on simple test chips lacking support circuitry for CDR and DFE adaptation functions.…”

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confidence: 99%

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

Bulzacchelli

Dickson

Deniz

et al. 2009

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers

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Extending data rates to meet the I/O needs of future computing and network systems is complicated by limited channel bandwidth. While a DFE [1] can be used to compensate channel distortion, its power dissipation reduces link energy efficiency, which is vitally important in complex systems. One way of reducing DFE power consumption is to use current-integrating summers [2][3][4][5]. Previously published current-integrating DFEs operating above 5Gb/s [3,5] were demonstrated on simple test chips lacking support circuitry for CDR and DFE adaptation functions. The architecture presented here includes additional data paths based on current-integrating summers to realize a fully integrated RX with CDR and continuous DFE adaptation. The design also features a digital calibration loop for setting the summer bias currents so that high performance is achieved over process variations and different data rates.The top-level RX architecture is shown in Fig. 21.6.1. The input data path is similar to that described in [1], except that a peaking amplifier is added to provide linear equalization which complements the operation of the DFE. The peaking amplifier, which uses a zero-peaked topology with switched capacitive degeneration, has 8 peaking settings, with a nominal range of 0-to-6dB at halfbaud frequency. The DFE uses a half-rate architecture; the tap weights for even and odd halves are adapted independently to improve tolerance against dutycycle distortion [6]. Half-rate clocks (C2) are generated by CML phase interpolators. Converting these clocks to CMOS rail-to-rail signals saves power in their distribution to the DFE, phase detector, and 2:8 DEMUX. In addition to the clocks (Clk D and Clk E ) used to sample the center and edges of the bits, a third clock (Clk A ) is generated which can be independently swept to monitor horizontal eye opening. An integrator calibration circuit provides operating point information to the integrator calibration logic which sets the integrator bias currents. The RX is powered from external analog (VDDA, nominally 1.2V) and digital (VDD, nominally 1.0V) supplies. A third supply VREG (nominally 1.0V) is generated from VDDA by a linear regulator with less than 40mVpp ripple; this supply is used to power noise-critical circuits, such as the CMOS C2 buffers within the DFE.The block diagram of a DFE half is shown in Fig. 21.6.2. The first DFE tap (H1) is realized by two-path speculation. This costs more area and power than a direct architecture [5], but ensures that all DFE feedback signals are fully established at the beginning of integration, improving summation accuracy. The two most critical DFE timing paths are the H2 feedback loop and the MUX select path. To meet timing constraints, these paths are realized in CML. A DCVS latch is used to convert CML to CMOS levels, so that the later tap (H3-H5) circuitry can be implemented in static CMOS to save power and area. The CML circuits are powered from VDDA; the DCVS and static CMOS circuits are powered from VREG. The path used for eye monitoring is...

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A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

Cited by 8 publications

References 6 publications

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z<inf>0</inf> at both TX and RX

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

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A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

Cited by 8 publications

References 6 publications

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4&#x00D7;Z<inf>0</inf> at both TX and RX

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

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A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z<inf>0</inf> at both TX and RX