A 3.3-mW ΣΔ modulator for UMTS in 0.18-μm CMOS with 70-dB dynamic range in 2-MHz bandwidth

Veldhoven, Robert H. M. van; Minnis, B.J.; Hegt, Hans; Roermund, Arthur van

doi:10.1109/jssc.2002.804329

Cited by 40 publications

(9 citation statements)

References 3 publications

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“…A 4-bit quantizer (15 comparators) clocked at 450 MHz is replaced by a 1.5-bit quantizer (two comparators) clocked at 780 MHz. Although a high f s requires a high bandwidth opamp, the 1.5-bit quantizer design has several attractive features [13]. The 1.5-bit quantizer decreases the quantization noise by about 6 dB, has a larger stable input range of 1.6 dB compared to a single-bit quantizer, and can be implemented with high linearity.…”

Section: δς Modulator Architecturementioning

confidence: 99%

5.2 mW 61 dB SNDR 15 MHz Bandwidth CT ΔΣModulator Using Single Operational Amplifier and Single Feedback DAC

Cho¹,

Park²,

Kim³

2016

ETRI J

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We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second-order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal-shape half-delayed return-to-zero feedback DAC eliminates the loop-delay compensation circuitry and improves pulse-delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of 0.098 mm 2 and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure-ofmerit of the modulator is 191 fJ/conversion-step.

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Section: δς Modulator Architecturementioning

confidence: 99%

5.2 mW 61 dB SNDR 15 MHz Bandwidth CT ΔΣModulator Using Single Operational Amplifier and Single Feedback DAC

Cho¹,

Park²,

Kim³

2016

ETRI J

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“…In the following, the used speed-accuracy-power trade-off for a continuous-time Σ∆ modulator P min,Σ∆CT is determined [38]. The key circuit building block in a CT Σ∆ modulator is the integrator, typically implemented as active RC-filters especially in the first stage [17,19,34,36,37,176]. Moreover, the integrators will dominate the power dissipation of the whole modulator.…”

Section: Low-power Limits In σ∆ Modulatorsmentioning

confidence: 99%

Continuous-Time Sigma-Delta A/D Conversion

2006

Springer Series in Advanced Microelectronics

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The Springer Series in Advanced Microelectronics provides systematic information on all the topics relevant for the design, processing, and manufacturing of microelectronic devices. The books, each prepared by leading researchers or engineers in their f ields, cover the basic and advanced aspects of topics such as wafer processing, materials, device design, device technologies, circuit design, VLSI implementation, and subsystem technology. The series forms a bridge between physics and engineering and the volumes will appeal to practicing engineers as well as research scientists. Microcontrollers in PracticeBy I. Susnea and M. Mitescu 19 Gettering Defects in Semiconductors

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“…With the emergence of new wireless communication standards, the circuitry in future personal wireless communication systems must support multiple operating modes, such as AMPS, GSM, CDMA, WCDMA, and UMTS [1,2,3]. A promising trend is to use reconfigurable receiver-on-achip that meets the resolution and bandwidth requirements of different communication standards [4].…”

Section: Introductionmentioning

confidence: 99%

“…(2) Design time, hence cost, is reduced. In reconfigurable ADCs, many blocks are shared between different modes.…”

Section: Introductionmentioning

confidence: 99%

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Systematic Methodology for Designing Reconfigurabl D S Modulator Topologies for Multimode Communication Systems

Wei

Tang

Doboli

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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This paper proposes a methodology for designing reconfigurable continuous-time ∆Σ modulator topologies. The methodology is based on the concept of generic topology that expresses all possible signal paths in a reconfigurable topology. Topologies are optimized for minimizing the complexity of the topologies, maximizing the sharing of circuitry for different modes, maximizing the topology robustness with respect to circuit nonidealities, and minimizing total power consumption. The paper presents a case study for designing topologies for a three mode reconfigurable ∆Σ modulator, and compares topologies with state-of-theart design.

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A 3.3-mW ΣΔ modulator for UMTS in 0.18-μm CMOS with 70-dB dynamic range in 2-MHz bandwidth

Cited by 40 publications

References 3 publications

5.2 mW 61 dB SNDR 15 MHz Bandwidth CT ΔΣModulator Using Single Operational Amplifier and Single Feedback DAC

5.2 mW 61 dB SNDR 15 MHz Bandwidth CT ΔΣModulator Using Single Operational Amplifier and Single Feedback DAC

Continuous-Time Sigma-Delta A/D Conversion

Systematic Methodology for Designing Reconfigurabl D S Modulator Topologies for Multimode Communication Systems

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