Citation for published version (APA): Veldhoven, van, R. H. M. (2003). A triple-mode continuous-time sigma delta modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver. Abstract-Time jitter in continuous-time 61 modulators is a known limitation on the maximum achievable signal-to-noise-ratio (SNR). Analysis of time jitter in this type of converter shows that a switched-capacitor (SC) feedback digital-to-analog converter (DAC) reduces the sensitivity to time jitter significantly. In this paper, an and continuous-time fifth-order 61 modulator with 1-bit quantizer and SC feedback DAC is presented, which demonstrates the improvement in maximum achievable SNR when using an SC instead of a switched-current (SI) feedback circuit. The modulator is designed for a GSM/CDMA2000/UMTS receiver and achieves a dynamic range of 92/83/72 dB in 200/1228/3840 kHz, respectively. The intermodulation distance IM2, 3 is better than 87 dB in all modes. Both the and modulator consumes a power of 3.8/4.1/4.5 mW at 1.8 V. Processed in 0.18-m CMOS, the 0.55-mm 2 integrated circuit includes a phase-locked loop, two oscillators, and a bandgap. Index Terms-Mobile communication, telecommunication receiver, intermediate frequency (IF) conversion, GSM, EDGE, CDMA2000, UMTS, sigma-delta analog-to-digital converter (ADC), sigma-delta modulator, switched-capacitor (SC) digital-to-analog converter (DAC), reduced jitter sensitivity.

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Feature-size scaling [1] of modern CMOS technologies dictated by Moore's law enables integration of extensive digital signal processing at low power consumption and small area. As the area of digital functions scales with s 2 and the f T is increasing with new technologies, the processing power of digital circuits per unit area is increasing. The area of analog functions however, does not scale. Instead, the new technologies bring lower supply and early voltages, which makes the analog design more difficult. This makes it attractive to replace analog functions by high-speed digital circuits where possible. The ΣΔ modulator presented in this paper exploits the advantages of new CMOS technologies by digitization on both architectural and circuit level. The target DR of the modulator is 77dB in 200kHz.

2002). A 3.3-m W sigma delta modular for UMTS in 0.18-m CMOS with 70-dB dynamic range in 2-MHz bandwidth. Abstract-A quadrature fourth-order, continuous-time, 61 modulator with 1.5-b quantizer and feedback digital-to-analog converter (DAC) for a universal mobile telecommunication system (UMTS) receiver chain is presented. It achieves a dynamic range of 70 dB in a 2-MHz bandwidth and the total harmonic distortion is 74 dB at full-scale input. When used in an integrated receiver for UMTS, the dynamic range of the modulator substantially reduces the need for analog automatic gain control and its tolerance of large out-of-band interference also permits the use of only first-order prefiltering. An IC including an and 61 modulator, phase-locked loop, oscillator, and bandgap dissipates 11.5 mW at 1.8 V. The active area is 0.41 mm 2 in a 0.18-m 1-poly 5-metal CMOS technology. Index Terms-1.5-b converter, 61ADC,telecommunicationreceiver, UMTS.