No abstract

An NPN-based temperature sensor with digital output transistors has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of ±0.5 • C (3σ) and a trimmed inaccuracy of ±0.2 • C (3σ) over the temperature range from −70 • C to 125 • C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e. correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 µA from a 1.2-V supply and occupies an area of 0.1 mm 2. I. INTRODUCTION Temperature sensors are used in a wide range of commercial applications, ranging from the control of domestic appliances and industrial machinery to environmental monitoring. Fabrication costs can be reduced by implementing the sensors in standard digital CMOS processes. This enables the co-integration of the read-out electronics, so that a digital temperature reading can be directly provided to, for instance, a microcontroller. This work is funded by the European Commission in the Marie Curie project TRANDSSAT-2005-020461.

Abstract-This work describes a method of implementing a fully-integrated Ultra-Low Power (ULP) radio for Wireless Sensor Networks (WSN). This is achieved using a specific Medium Access Control (MAC) protocol, employing a dutycycled wake-up radio and a crystal-less clock generator, and an ad-hoc modulation scheme (Impulse Radio) with a bandwidth of 17.7 MHz in the 2.4 GHz -ISM band. The total average power consumption is expected to be less than 100 μW.

No abstract

This paper describes a 2.4GHz Wake-up Receiver (WuRx) designed to operate with low-accuracy (<0.5%) frequency references [1], enabling crystal-less and thus low-cost wireless sensor nodes (WSNs). Robustness to frequency error is achieved by combining non-coherent energy detection with a broadband-IF superheterodyne architecture, and by using a pulse-position-modulated (PPM) impulse radio (IR) modulation scheme [2]. The Rx front-end and the LO generator are duty-cycled at pulse level, thereby reducing the power consumption to less than 420µW, which is more than adequate for use in WSNs [2]. PPM-IR also enables the realization of an interferer-robust receiver without the use of bulky off-chip RF filters [3,4]. This 65nm CMOS fully integrated WuRx employs a dutycycled LO generator and achieves a sensitivity of -82dBm at a data rate of 500kb/s with an energy efficiency of 830pJ/bit. Figure 11.6.1 shows the frequency plan of the proposed WuRx. The PPM-IR RF input signal has a nominal center frequency of 2.44GHz and is down-converted to IF by a 2.39GHz LO. Since the LO frequency is derived from a frequency reference with an inaccuracy of <0.5%, the actual LO frequency will lie between 2.38GHz and 2.40GHz. The transmitted signal from a similar WSN will also have a 0.5% frequency error and so the IF signal will lie somewhere between 26MHz and 74MHz. Signals in this IF band are amplified and then downconverted to baseband by a full-wave rectifier. The use of a broadband IF amplifier and the non-coherent energy detection of the incoming RF pulses, make it possible to tolerate the IF uncertainty. The extra gain needed for efficient energy detection can be provided at IF with greater power savings and higher sensitivity than RF diode detectors [4,5]. However, heterodyne architectures typically require the generation of a high-frequency LO, dominating their power budget [6]. Alternatively, a periodically calibrated free-running digitally-controlled oscillator (DCO) can be used [3]. However, temperature and supply voltage variations may cause unpredictable frequency drift. Here, the DCO is embedded in a duty-cycled PLL (DCPLL) to overcome these issues [7]. The closed-loop nature of the DCPLL prevents frequency drift, while power efficiency is achieved by burst-mode operation.Figure 11.6.2 depicts the block diagram of the WuRx comprising an Rx chain and a DCPLL-based LO generator. The differential RF input signal is PPM at 500kb/s with a pulse width of 80ns and a center frequency of 2.44GHz. A finitestate machine (FSM) driven by a 10MHz reference clock (with an inaccuracy of <0.5%) duty cycles the DCO, the mixer and the IF amplifier. The DCO only operates during one reference clock cycle, i.e. 100ns, and is in sleep mode for the next nine, i.e. 900ns. This translates into a 10% duty-cycled DCPLL with the 1MHz pulse repetition rate required to downconvert and detect the pulse positions of the input signal. In the receiver, this duty cycling translates into significant power savings. As in [7], the DCO consists of a current-contr...