A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer

Abstract

Abstract:We explore a dual-band fractional-N PLL synthesizer with 3.5 mW, 5 μsec settling time and 15 μsec start-up time in 0.18 μm CMOS technology. The power consumption is minimized through the design efforts in LC-VCO design to maximize the quality factor of an integrated inductor up to 6.1 at 866 MHz and minimize the VCO gain by a capacitor tuning technique with an on-chip nonvolatile memory and the proper choice of varactor. Measured results of a prototype fractional-N PLL satisfy the required settling and start-up times, and indicate that the phase noises at 10 kHz and 100 KHz offset are −108.7 dBc/Hz and −98.3 dBc/Hz, respectively, and the reference spurious level is −81.6 dBc.

A 0.7V 1.6mW fractional-N synthesizers for BLE RF transceiver in 40nm CMOS

“…The fractional-N RF synthesizer is essential to wireless communication systems. It is required to generate a low phase noise and low spur LO while achieving low power consumption [1,2,3,4,5,6,7,8]. Reducing the supply voltage is an effective way to reduce power consumption.…”