A 3.75Gb/s CML output driver with configurable pre-emphasis in 65nm CMOS technology

Fu, Yong; Wen, Zhenchao; Chen, Lei

doi:10.1145/3018009.3018048

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“…The resulting continuous-time transfer function is given by H( f ) = c 0 + N i=1 c i exp −i2πf i j=1 τ j and should have a high-pass response. Conventional FFE implementations constrain the delays to τ i = 1/f clk = 1 × UI where f clk is the clock frequency and 1/f clk is the unit interval (UI) [3]. In this case, H(f) is periodic with a period of f clk , so the desired high-pass response is only obtained over a limited frequency range (up to 1/(2f clk )).…”

Section: Introductionmentioning

confidence: 99%

A low-power 1 Gb/s line driver with configurable pre-emphasis for lossy transmission lines

et al. 2023

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A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval via an 8-stage delay-locked loop and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.

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Section: Introductionmentioning

confidence: 99%