A 3.9-4.7 GHz 0.35 mW DCO with −187.4 dBc FoM in 28nm CMOS

Levinger, R.; Levi, Roi; Shumaker, Evgeny; Levin, Scott R.; Horovitz, G.

doi:10.23919/eumic.2018.8539952

Cited by 9 publications

(6 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The [10] is based on the schematic simulation, hence the FOM jitter is better than the proposed designs. The DCO in [11] is designed using 28 nm technology and it uses LC-tank based architecture. Hence, the phase noise performance of [11] is better than the DAC-based and controller-based DCO.…”

Section: Layout and Simulation Resultsmentioning

confidence: 99%

“…The DCO in [11] is designed using 28 nm technology and it uses LC-tank based architecture. Hence, the phase noise performance of [11] is better than the DAC-based and controller-based DCO. However, its active area is much larger than the proposed DAC-based and controller-based DCO in spite of the DCO that was implemented in 28 nm.…”

Section: Layout and Simulation Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

2021

View full text Add to dashboard Cite

This paper presents a comparative study between two different implementations of digitally-controlled-oscillators (DCOs), whcih is the DAC-based and the digital controller-based DCO in TSMC 65 nm CMOS technology. This paper focuses on ring-oscillator architectures due to their high stability against PVT. The DAC-based oscillator implements a differential architecture, and the digital controller-based architecture operates in a single-ended signal. The SFDR of the DAC-based DCO is 77.2 dBc and controller-based DCO is 56.8 dBc at 125 MHz offset. The Monte-Carlo simulation gives a deviation of 7.4% and 8.5% for the DAC-based and controller-based DCO, respectively. The phase noise performance of the DAC-based DCO and controller-based DCO is −78.9 dBc/Hz and −81.3 dBc/Hz at 1 MHz offset, respectively. The implementations are given and compared according to their performance based on post-layout simulation results.

show abstract

Section: Layout and Simulation Resultsmentioning

confidence: 99%

Section: Layout and Simulation Resultsmentioning

confidence: 99%

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

2021

View full text Add to dashboard Cite

show abstract

“…Another research in DCO adds coarse, medium, and fine-tuned switched-capacitor (SC) arrays to the traditional inductorcapacitor oscillator to achieve high resolution. [11][12][13][14][15][16][17][18] Luong presented a 54.79-63. 16 GHz DCO using an exponentially scaling SC ladder.…”

Section: Introductionmentioning

confidence: 99%

“…[11][12][13][14][15][16][17][18] Luong presented a 54.79-63. 16 GHz DCO using an exponentially scaling SC ladder. The measured resolution is 300 kHz, and the phase noise is less than À90.7 dBc/Hz, 11 whereas the DCO is still sensitive to substrate noise.…”

Section: Introductionmentioning

confidence: 99%

A 3.83–5.55 GHz high frequency resolution DCO with optimized switched‐capacitor ladder and low‐coupled eight‐shaped transformer

Zou

Cheng

et al. 2023

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryA high frequency resolution digitally controlled oscillator (DCO) is proposed for wireless transceivers, in which the scheme adopts an optimized cascaded differential switched‐capacitor (SC) ladder and a low‐coupled eight‐shaped transformer. The frequency resolution is further improved by the low electromagnetic coupling effect between the primary and secondary coils of the on‐chip transformer, thus reducing quantization noise and phase noise. An eight‐shaped transformer designed using two coils cross‐connected each other is adopted to reduce the magnetic coupling and frequency pulling. The proposed DCO is implemented in a TSMC 180‐nm CMOS process, and a tuning range of 36.7% from 3.83 to 5.55 GHz with a frequency resolution of 17 kHz is achieved. The phase noise is −120.29 dBc/Hz at 1 MHz offset from the 3.83 GHz carrier frequency. The DCO consumes 9.26 mA from a 1.8 V supply, while the figure of merit with tuning range is −191 dBc/Hz. The chip size is 0.294 mm2.

show abstract

“…Submikroninėse technologijose kai kurių pagamintų SVG plotas nėra pateiktas. Nanometrinėse technologijose pagamintų ĮVG plotas kinta nuo 0,02 mm 2(Zhang & Otto, 2017) (22 nm technologija) ir(Levinger et al, 2018) (28 nm technologija) iki 0,65 mm 2 (40 nm technologija).Lyginant ĮVG ir SVG maksimalius plotus matoma, kad ĮVG maksimalus plotas yra 1,06 mm 2 tuo tarpu SVG maksimalus plotas yra 0,65 mm 2 . Iš čia galima teigti, kad maksimalus SVG plotas yra 36,3 % mažesnis nei maksimalus ĮVG užimamas plotas.…”

unclassified

Nanometrinių ir submikroninių integrinių grandynų įtampa ir skaitmeniniu būdu valdomiems generatoriams kūrimas ir tyrimas

Mačaitis¹

2019

View full text Add to dashboard Cite

Disertacija rengta 2015-2019 metais Valstybiniame mokslinių tyrimų institute Fizinių ir technologijos mokslų centre. Vadovas prof. habil. dr. Romualdas NAVICKAS (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001). Vilniaus Gedimino technikos universiteto elektros ir elektronikos inžinerijos mokslo krypties disertacijos gynimo taryba: Pirmininkas prof. dr. Šarūnas PAULIKAS (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001). Nariai: dr. Alvydas LISAUSKAS (Lenkijos mokslų akademijos Aukšto slėgio fizikos institutas, fizika -N 002), dr. Vitalij NOVICKIJ (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001), dr. Česlovas ŠIMKEVIČIUS (Valstybinis mokslinių tyrimų institutas Fizinių ir technologijos mokslų centras, elektros ir elektronikos inžinerija -T 001), prof. dr. Algimantas VALINEVIČIUS (Kauno technologijos universitetas, elektros ir elektronikos inžinerija -T 001). Disertacija bus ginama viešame Elektros ir elektronikos inžinerijos mokslo krypties disertacijos gynimo tarybos posėdyje 2019 m. lapkričio 8 d. 13 val. Valstybinio mokslinių tyrimų instituto Fizinių ir technologijos mokslų centro posėdžių salėje D401.

show abstract

A 3.9-4.7 GHz 0.35 mW DCO with −187.4 dBc FoM in 28nm CMOS

Cited by 9 publications

References 5 publications

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

A 3.83–5.55 GHz high frequency resolution DCO with optimized switched‐capacitor ladder and low‐coupled eight‐shaped transformer

Nanometrinių ir submikroninių integrinių grandynų įtampa ir skaitmeniniu būdu valdomiems generatoriams kūrimas ir tyrimas

Contact Info

Product

Resources

About