A 30-GHz Digital Sub-Sampling Fractional-$N$  PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS

Bertulessi, Luca; Karman, Saleh; Cherniak, Dmytro; Garghetti, Alessandro; Samori, Carlo; Lacaita, A.L.; Levantino, Salvatore

doi:10.1109/jssc.2019.2940332

Cited by 26 publications

(5 citation statements)

References 26 publications

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“…As shown in Fig. 7(c), the CM current enters the inductive path in all the cases (in both the ω L and ω H modes), while the third-harmonic DM current entering the 9 This can be roughly modeled by periodically modulated transconductance G m and drain current I D ; hence, it mainly depends on V GS around the saturation region of MOS transistor (e.g., large V GS with large I 1/ f, rms ) [54]. 10 Sharper rising or falling edges in V DS are more robust to noise (i.e., presenting the narrow (in time) and small (in magnitude) h DS in these edges), while its less steep edges (also implying longer noise exposure time) are more vulnerable to noise (i.e., showing wide and large h DS ).…”

Section: B Flicker Pn Reduction By Negative Phase Shiftmentioning

confidence: 83%

“…signal in supporting the complex modulation schemes (e.g., 256-or 1024-QAM) [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12]. At the same time, with the signal bandwidths reaching 800 MHz in the 5G mm-wave bands, direct conversion transmitters and receivers are preferred.…”

Section: Table I Specifications Of Irr and Its Corresponding Evmmentioning

confidence: 99%

“…The flicker PN (caused by a single MOS transistor, e.g., M 1 in Fig. 3) is calculated as follows: (10) where I 1/ f, rms (t) 9 (unit: A/ √ Hz) is the periodically modulated rms value of the flicker noise current at a low offset frequency ω (e.g., 2π × 10 kHz), T 0 (=2π/ω 0 ) is the oscillation period, and h DS (t) (unit: rad/C) is the non-normalized ISF [75] associated with V DS , describing the phase response of V DS against current impulse perturbations. 10 The intuitive understanding and simulation methods of I 1/ f,rms (t) and h DS (t) [based on the periodic transfer function (PXF)] were provided in [55] and [73] for numerical verification according to (10).…”

Section: A Flicker Noise Upconversion In ω L and ω H Modesmentioning

confidence: 99%

See 2 more Smart Citations

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Chen

Siriburanon

et al. 2023

IEEE J. Solid-State Circuits

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In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A third transformer coil is added for the inter-core coupling with the source terminals of the switching transistors. We identify that the inter-core coupling in quadrature oscillators causes an asymmetric flicker noise current, thus degrading flicker PN. As a remedy, we propose a deliberate drain-to-gate phase shift of the switching transistors by means of capacitive loading to fix this asymmetry. The ±90 • I/Q mode ambiguity is also resolved by introducing another phase shift in the source-coupling; it is explained by a simplified analysis with phasor diagrams. Fabricated in the TSMC 28-nm LP CMOS, the prototype achieves PN of −112 dBc/Hz and figure-of-merit (FoM) of −185 dB at 1-MHz offset of 25.7 GHz. The measured flicker PN corner is 140-250 kHz and image rejection ratio (IRR) >47 dB over the whole 18% tuning range (TR). To the best of the authors' knowledge, it is the best reported PN and IRR for a mm-wave quadrature oscillator.

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Section: B Flicker Pn Reduction By Negative Phase Shiftmentioning

confidence: 83%

Section: Table I Specifications Of Irr and Its Corresponding Evmmentioning

confidence: 99%

Section: A Flicker Noise Upconversion In ω L and ω H Modesmentioning

confidence: 99%

See 1 more Smart Citation

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Chen

Siriburanon

et al. 2023

IEEE J. Solid-State Circuits

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“…The clock frequency multiplier has many applications in integrated circuits, especially for modern system-on-chip (SoC) designs [1]. In general, there are a few methods to realize frequency multiplication: phase-locked loops (PLLs) [2][3][4], delay-locked loops (DLLs) [5][6][7][8], and clock phase interpolation [9][10][11][12]. PLLs and DLLs offer good solutions for accurate clock generation; however, they generally require a long time to lock or settle due to the feedback operation.…”

Section: Introductionmentioning

confidence: 99%

A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction

et al. 2023

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This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock phases while reducing the input clock phase noise at the same time. A new delay line circuit is also proposed for improving power supply rejection. In addition, to improve the matching quality as well as the end-effects tolerance of the on-chip capacitors, a single-value series/parallel algorithm is proposed. Designed in a 0.18 μm digital CMOS process, with a 20 MHz input clock frequency, the multiplier achieves a multiplication factor of 5 with a lock-in time of less than 4 clock cycles. The input clock jitter is reduced from 7ns RMS to 153 ps RMS after frequency multiplication.

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“…Subsampling PLL (SSPLL) is promising to achieve low in-band phase noise without divider [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37]. The intrinsically high gain of the subsampling phase detector (SSPD) can suppress in-band phase noise significantly.…”

mentioning

confidence: 99%

A 21.8–41.6-GHz Low Jitter and High FoM$_{\bm{j}}$ Fast-Locking Subsampling PLL With Dead Zone Automatic Controller

Chen,

Shu,

Yin

et al. 2024

IEEE Trans. Microwave Theory Techn.

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In this article, a wideband millimeter-wave (mm-wave) fast-locking subsampling phase-locked loop (FL-SSPLL) with low jitter and high jitter-power figure of merit (FoM j ) is proposed. A quadrature subsampling phase detector (QSSPD)-based dead zone automatic controller (DZAC) is introduced for fast locking. Such DZAC eliminates the long locking time caused by the dead zone of frequency-locked loop (FLL) while maintaining low in-band phase noise of subsampling loop (SSL). The mm-wave quad-mode oscillator is integrated in the FL-SSPLL to achieve a wide frequency range. The proposed FL-SSPLL is fabricated in a 40-nm CMOS technology and occupies a core area of 0.18 mm 2 . Measurements exhibit a wide output frequency range of 62.5% from 21.8 to 41.6 GHz with a 100-MHz reference. The FL-SSPLL achieves a 62.7-79.1-fs root-mean-square (rms) jitter across the whole frequency range. The total power consumption is 18.3-23.6 mW, leading to FoM j from −248.3 to −251.4 dB. Meanwhile, the FL-SSPLL features a robust lock acquisition and achieves less than 1.5-µs locking time.

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A 30-GHz Digital Sub-Sampling Fractional-$N$ PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS

Cited by 26 publications

References 26 publications

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction

A 21.8–41.6-GHz Low Jitter and High FoM$_{\bm{j}}$ Fast-Locking Subsampling PLL With Dead Zone Automatic Controller

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