This paper presents a mmW frequency generation stage aimed at minimizing phase noise via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A second-harmonic resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for explicit common-mode current return path. Class-F operation with third-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10 GHz tank at the 30 GHz frequency generation. We further propose a comprehensive quantitative analysis method of flicker noise upconversion mechanism exploiting latest insights into the flicker noise mechanisms in nanoscale short-channel transistors. The method is numerically verified against foundry models. The proposed 27.3-31.2 GHz oscillator is implemented in TSMC 28 nm CMOS. It achieves phase noise of -106 dBc/Hz at 1 MHz offset and figure-of-merit (FoM) of -184 dBc/Hz at 27.3 GHz. Its flicker phase-noise (1/f 3 ) corner of 120 kHz is an order-ofmagnitude better than currently achievable at mmW.

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This brief aims to intuitively explain and numerically verify the observed phenomenon of flicker noise reduction in oscillators of reduced conduction angle (i.e., in class-C), which has been presented in literature but never properly explained. The flicker phase noise in a voltage-biased oscillator capable of operating in class-B and class-C is compared and numerically verified using a commercial simulation model of TSMC 28-nm CMOS. We illustrate how narrowing the conduction angle can suppress the 1/f noise up-conversion by decreasing 1/f noise exposure to the asymmetric rising and falling edges of oscillation waveform. The effects of implicit common-mode tank in the class-C operation is also discussed. We further clarify ambiguities among several simulation methods of impulse sensitivity function (ISF) based on periodic small-signal analysis (PAC or PXF), which is a key tool in understanding the flicker noise upconversion. A clearer ISF simulation method based on positive sidebands of PXF is proposed.

This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate z-domain model, supporting any frequency division ratio N and CSL (or IL) strength β. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its "loop" bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the "loop" cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75-26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.