A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Abstract

This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate z-domain model, supporting any frequency division ratio N and CSL (or IL) strength β. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its "loop" bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the "loop" cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75-26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.

Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial

“…To bridge from the high (i.e., f osc ) to low (i.e., f ref ) sampling-rate timestamps, we point out the intrinsic oscillator downsampling [see Fig. 1(b)] taking place in all phaselocked systems, including divider-based PLLs (e.g., chargepump PLLs (CP-PLLs) [33]), divider-less PLLs (e.g., alldigital PLLs (ADPLLs) [30], [34] or sub-sampling PLLs (SS-PLLs) [4]), and CSL/IL [2]. Accordingly, we have [2]:…”

“…1(b)] taking place in all phaselocked systems, including divider-based PLLs (e.g., chargepump PLLs (CP-PLLs) [33]), divider-less PLLs (e.g., alldigital PLLs (ADPLLs) [30], [34] or sub-sampling PLLs (SS-PLLs) [4]), and CSL/IL [2]. Accordingly, we have [2]:…”

“…where T osc (z osc ) is the z-transform of t osc [k], while its spectral replicas due to downsampling are neglected. 1 The PN of 1 A detailed discussion of PN folding by downsampling causing the oscillator PN increasing 3 dB beyond the "loop" cutoff frequency in ideal CSL/IL is presented in [2], culminating in [2, Fig. 7…”

“…2(b). 2 It focuses on the time-to-digital converter (TDC) based on an analog-to-digital converter (ADC) and digital loop filter with proportional (i.e., α) and integral (i.e., ρ) paths.…”

“…A FREQUENCY synthesizer of ultra-low jitter (i.e., sub-50 fs) is a key block to enable the emerging 5G/6G wireless and other high-speed communication standards [1]- [3]. There are two main routes being pursued towards achieving such tough jitter performance: high-bandwidth PLLs with a high phase-detector (PD) gain [4]- [14], and injection-locking (IL) [15]- [24] or a recently introduced generalization of it, charge-sharing locking (CSL) [2], [25]. It is becoming increasingly obvious that the phase noise (PN) modeling in these high-bandwidth techniques must be radically different from what is currently used in the regular-bandwidth PLLs (e.g., s-domain).…”