A low jitter sub‐sampling phase‐locked loop with sampling thermal noise cancellation technique

Abstract

The traditional sub‐sampling phase‐locked loop faces the tradeoffs between phase noise and spur, in that low in‐band phase noise requires large sampling capacitor size but at the sacrifice of spur performance. This paper presents a sub‐sampling PLL aimed at minimizing in‐band phase noise via sampling thermal noise cancellation technique. It enables the substantial reduction of in‐band phase noise while reducing the sampling capacitor size. In addition, due to the reduction of the sampling capacitance, the reference spur performance of the PLL is improved, and the power consumption of the isolation buffer is reduced. Implemented in a 65 nm CMOS process, the in‐band phase noise at 200 kHz offset is −133.4 dBc/Hz at 2.2 GHz and integrated jitter is 80 fsrms. The reference spur is −67 dBc. It consumes 5.5 mA from 1.2 V supply and occupies 0.72 mm2.