The traditional sub‐sampling phase‐locked loop faces the tradeoffs between phase noise and spur, in that low in‐band phase noise requires large sampling capacitor size but at the sacrifice of spur performance. This paper presents a sub‐sampling PLL aimed at minimizing in‐band phase noise via sampling thermal noise cancellation technique. It enables the substantial reduction of in‐band phase noise while reducing the sampling capacitor size. In addition, due to the reduction of the sampling capacitance, the reference spur performance of the PLL is improved, and the power consumption of the isolation buffer is reduced. Implemented in a 65 nm CMOS process, the in‐band phase noise at 200 kHz offset is −133.4 dBc/Hz at 2.2 GHz and integrated jitter is 80 fsrms. The reference spur is −67 dBc. It consumes 5.5 mA from 1.2 V supply and occupies 0.72 mm2.

A Ka-band low noise amplifier (LNA) is presented that improves the traditional source-degeneration LNA by utilizing broadband transformer matching and gate-drain feedback technology. The proposed LNA achieves an ultra-wideband LNA while maintaining the advantages of high integration and low power consumption of the traditional source-degeneration LNA. In addition, cascade technology is adopted to further improve peak gain. The proposed LNA is implemented in 55nm CMOS process. The simulated results show that the LNA achieves stable gain response in the 21.7-36.5 GHz frequency band, with a peak power gain of 20.8 dB. The minimum noise coefficient is 4.4 dB, and the DC power consumption is 15 mW. The LNA achieves a compact chip area of 0.33 mm .